SPI_HOST Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 17.133m 15.001ms 38 50 76.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 17.192us 5 5 100.00
V1 csr_rw spi_host_csr_rw 2.000s 15.459us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 1.391ms 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 49.322us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 23.144us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 2.000s 15.459us 20 20 100.00
spi_host_csr_aliasing 3.000s 49.322us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 20.224us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 24.063us 5 5 100.00
V1 TOTAL 103 115 89.57
V2 performance spi_host_performance 8.000s 32.445us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 55.000s 4.060ms 50 50 100.00
spi_host_error_cmd 8.000s 60.807us 50 50 100.00
spi_host_event 15.567m 23.416ms 50 50 100.00
V2 clock_rate spi_host_speed 11.567m 10.001ms 37 50 74.00
V2 speed spi_host_speed 11.567m 10.001ms 37 50 74.00
V2 chip_select_timing spi_host_speed 11.567m 10.001ms 37 50 74.00
V2 sw_reset spi_host_sw_reset 10.250m 15.004ms 34 50 68.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 558.942us 50 50 100.00
V2 cpol_cpha spi_host_speed 11.567m 10.001ms 37 50 74.00
V2 full_cycle spi_host_speed 11.567m 10.001ms 37 50 74.00
V2 duplex spi_host_smoke 17.133m 15.001ms 38 50 76.00
V2 tx_rx_only spi_host_smoke 17.133m 15.001ms 38 50 76.00
V2 stress_all spi_host_stress_all 16.700m 22.501ms 40 50 80.00
V2 spien spi_host_spien 11.433m 10.001ms 42 50 84.00
V2 stall spi_host_status_stall 7.700m 10.006ms 42 50 84.00
V2 Idlecsbactive spi_host_idlecsbactive 12.800m 200.000ms 38 50 76.00
V2 data_fifo_status spi_host_overflow_underflow 55.000s 4.060ms 50 50 100.00
V2 alert_test spi_host_alert_test 7.000s 52.607us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 58.276us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 166.278us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 166.278us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 17.192us 5 5 100.00
spi_host_csr_rw 2.000s 15.459us 20 20 100.00
spi_host_csr_aliasing 3.000s 49.322us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 92.812us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 17.192us 5 5 100.00
spi_host_csr_rw 2.000s 15.459us 20 20 100.00
spi_host_csr_aliasing 3.000s 49.322us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 92.812us 20 20 100.00
V2 TOTAL 623 690 90.29
V2S tl_intg_err spi_host_tl_intg_err 3.000s 138.158us 20 20 100.00
spi_host_sec_cm 7.000s 252.336us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 3.000s 138.158us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 54.750m 100.004ms 4 10 40.00
TOTAL 755 840 89.88

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.77 95.70 100.00 95.07 90.87

Failure Buckets

Past Results