6a84251492| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 17.133m | 15.001ms | 38 | 50 | 76.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 17.192us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 2.000s | 15.459us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 1.391ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 49.322us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 23.144us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 2.000s | 15.459us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 49.322us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 20.224us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 2.000s | 24.063us | 5 | 5 | 100.00 |
| V1 | TOTAL | 103 | 115 | 89.57 | |||
| V2 | performance | spi_host_performance | 8.000s | 32.445us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 55.000s | 4.060ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 8.000s | 60.807us | 50 | 50 | 100.00 | ||
| spi_host_event | 15.567m | 23.416ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.567m | 10.001ms | 37 | 50 | 74.00 |
| V2 | speed | spi_host_speed | 11.567m | 10.001ms | 37 | 50 | 74.00 |
| V2 | chip_select_timing | spi_host_speed | 11.567m | 10.001ms | 37 | 50 | 74.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.250m | 15.004ms | 34 | 50 | 68.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 558.942us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.567m | 10.001ms | 37 | 50 | 74.00 |
| V2 | full_cycle | spi_host_speed | 11.567m | 10.001ms | 37 | 50 | 74.00 |
| V2 | duplex | spi_host_smoke | 17.133m | 15.001ms | 38 | 50 | 76.00 |
| V2 | tx_rx_only | spi_host_smoke | 17.133m | 15.001ms | 38 | 50 | 76.00 |
| V2 | stress_all | spi_host_stress_all | 16.700m | 22.501ms | 40 | 50 | 80.00 |
| V2 | spien | spi_host_spien | 11.433m | 10.001ms | 42 | 50 | 84.00 |
| V2 | stall | spi_host_status_stall | 7.700m | 10.006ms | 42 | 50 | 84.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 12.800m | 200.000ms | 38 | 50 | 76.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 55.000s | 4.060ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 7.000s | 52.607us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 58.276us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 166.278us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 166.278us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 17.192us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 2.000s | 15.459us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 49.322us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 92.812us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 17.192us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 2.000s | 15.459us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 49.322us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 92.812us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 623 | 690 | 90.29 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 138.158us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 7.000s | 252.336us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 138.158us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 54.750m | 100.004ms | 4 | 10 | 40.00 | |
| TOTAL | 755 | 840 | 89.88 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.77 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 38 failures:
0.spi_host_spien.36802211005918268752021923517106451796001462127403151115128716962143107543298
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 10001073705 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb43e18d4) == 0x0
UVM_INFO @ 10001073705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_spien.72829340243057971028999470787000727588706174083614568693731885125138206370548
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_spien/latest/run.log
UVM_FATAL @ 10000761081 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xeed695d4) == 0x0
UVM_INFO @ 10000761081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
1.spi_host_speed.107821064065898398752288007411907820426449946198148418932098867253149355334291
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_speed/latest/run.log
UVM_FATAL @ 10000956364 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x724f4654) == 0x0
UVM_INFO @ 10000956364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_speed.75470307155293173044898277457175734573175495735922385862044738647592426742572
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_speed/latest/run.log
UVM_FATAL @ 10004632384 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe59d65d4) == 0x0
UVM_INFO @ 10004632384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
2.spi_host_upper_range_clkdiv.2469634750737489750416451296295045831521915565081857195233733725592864453389
Line 311, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003320167 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5479ab54) == 0x0
UVM_INFO @ 100003320167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_upper_range_clkdiv.70404925917685771485156064349927764788166886865267823204793254760878009028442
Line 337, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004071457 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe290ad54) == 0x0
UVM_INFO @ 100004071457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
2.spi_host_sw_reset.33396829000387373501846538603316557718768548236296548860172696987930993287766
Line 338, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10004458997 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x11ebfad4) == 0x0
UVM_INFO @ 10004458997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_sw_reset.78882460896371601719388995292013630559275116928766702058976835445808204026702
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10029643959 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbedac854) == 0x0
UVM_INFO @ 10029643959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
3.spi_host_stress_all.72690592638251965373971999426435151522448666522960673786948906253376068207283
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10001637334 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8c0f4f14) == 0x0
UVM_INFO @ 10001637334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_stress_all.31651090000258455537527029596976706009750823894217945242465184040777141749252
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22501339121 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe3bcbf14) == 0x0
UVM_INFO @ 22501339121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 15 failures:
Test spi_host_upper_range_clkdiv has 1 failures.
0.spi_host_upper_range_clkdiv.84075200283963123857330948682563692516045915176920878807834564114205633206596
Line 337, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003903624 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb4a40454) == 0x0
UVM_INFO @ 100003903624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 3 failures.
9.spi_host_speed.11135595984979305568290854857500822693988573765534501981037381052650819767030
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_speed/latest/run.log
UVM_FATAL @ 10004662955 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7741f554) == 0x0
UVM_INFO @ 10004662955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_speed.85179406855799532697261795139505945141424001347313239538015119800626158063260
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_speed/latest/run.log
UVM_FATAL @ 10003303135 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3a0c714) == 0x0
UVM_INFO @ 10003303135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_sw_reset has 1 failures.
9.spi_host_sw_reset.97826314820379134173324787428179254568205866576905886433474711889905141869957
Line 714, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10065468696 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf1d50d14) == 0x0
UVM_INFO @ 10065468696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 5 failures.
12.spi_host_stress_all.91195466425029479755693042522632457978248269439482830328343532159704899592063
Line 426, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22697577405 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x78f32d54) == 0x0
UVM_INFO @ 22697577405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_host_stress_all.40323168347626385421389258690912080167156484263757608774201721990551427061855
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15010215953 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf48bae94) == 0x0
UVM_INFO @ 15010215953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_spien has 1 failures.
19.spi_host_spien.111227875446764131477978514658517977993161589116611642852883466612974356502493
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_spien/latest/run.log
UVM_FATAL @ 10001038964 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x148ad794) == 0x0
UVM_INFO @ 10001038964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 14 failures:
Test spi_host_sw_reset has 3 failures.
10.spi_host_sw_reset.27849336790016855054165030032112090381792641555634772937550118981383520646097
Line 342, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001328678 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x69aa0394) == 0x1
UVM_INFO @ 10001328678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_host_sw_reset.51829050643113743408518857629855123077402803621613768619748525987629711201413
Line 411, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10094472549 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4a0f6914) == 0x1
UVM_INFO @ 10094472549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_status_stall has 6 failures.
11.spi_host_status_stall.112350207976538312229133821871361062045496604196025456123725592807917115209897
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15031071723 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4de64f54) == 0x1
UVM_INFO @ 15031071723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_host_status_stall.79104471243172805020267546285350531938868741345016829712533553774231933596281
Line 925, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10200562750 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9cbef994) == 0x1
UVM_INFO @ 10200562750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_speed has 3 failures.
16.spi_host_speed.12981288026944405280015610878521261637635611389162966443879301379619286195570
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_speed/latest/run.log
UVM_FATAL @ 10130976202 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf556dcd4) == 0x1
UVM_INFO @ 10130976202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_host_speed.10819961800516998639511464849844279438117324313633774807342156788612143204295
Line 395, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_speed/latest/run.log
UVM_FATAL @ 10016163573 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4bc5e354) == 0x1
UVM_INFO @ 10016163573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_smoke has 1 failures.
33.spi_host_smoke.985246399447877293400280388734391938764128583426079616957331820281641053820
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_smoke/latest/run.log
UVM_FATAL @ 15210047014 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe0dfacd4) == 0x1
UVM_INFO @ 15210047014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
41.spi_host_spien.6569058287407322320902611214720196607985007077489875132775549007981611914846
Line 473, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_spien/latest/run.log
UVM_FATAL @ 10010753883 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7aff8914) == 0x1
UVM_INFO @ 10010753883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 6 failures:
10.spi_host_idlecsbactive.66257559925233279662616926405103208197681885395440288790923469633181480840015
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10003521983 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4569bb14) == 0x0
UVM_INFO @ 10003521983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_idlecsbactive.44932927310885136180264931306366328239873940433267207623046913439306184893058
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10019012576 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2647ed14) == 0x0
UVM_INFO @ 10019012576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
7.spi_host_idlecsbactive.63267326786891753824652653773771056021643223354363516984273422582814407188692
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10020183863 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd9006914) == 0x0
UVM_INFO @ 10020183863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_idlecsbactive.11705872347018750055497901749823861496452163105072220154336233144238648957268
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004899703 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcbb6ab94) == 0x0
UVM_INFO @ 10004899703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 3 failures:
Test spi_host_sw_reset has 2 failures.
1.spi_host_sw_reset.38324379965893593097653121950401797641748890985296749340211343263061487739747
Line 346, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10004110656 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x34cab414) == 0x1
UVM_INFO @ 10004110656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_host_sw_reset.91573661758682900943038064832189974412053609333557252436905270483308188676431
Line 443, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10255911347 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc5c67654) == 0x1
UVM_INFO @ 10255911347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
34.spi_host_status_stall.74884707242311800929778925699681614347271014018213984887636891284094268630859
Line 421, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10274678378 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9c24bed4) == 0x1
UVM_INFO @ 10274678378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
4.spi_host_upper_range_clkdiv.114260234743622164365453209856733492596449327873859356979809200531568607362634
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:26d1bf60-df70-4d3c-a653-c13908ef9eac
7.spi_host_upper_range_clkdiv.103344932649539784736964326666490515910173264214071237859887891649784145494814
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:8ed37842-926a-4dc8-abd0-9817dc6e8840
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
28.spi_host_idlecsbactive.51980404537224396989316731488655319051933235797504277980997196034570468361439
Line 407, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_host_idlecsbactive.27336846173333943919895181736689951867409407468434113431059444733879318491050
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:
38.spi_host_status_stall.109985748538661867337932697135549460372431126878246379282943232236146462501394
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
UVM_ERROR @ 5063221 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5063221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---