39211701b5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 9.317m | 15.001ms | 43 | 50 | 86.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 108.412us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 21.894us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 6.000s | 161.111us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 22.149us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 176.713us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 21.894us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 22.149us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 16.320us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 65.358us | 5 | 5 | 100.00 |
| V1 | TOTAL | 108 | 115 | 93.91 | |||
| V2 | performance | spi_host_performance | 8.000s | 53.059us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.383m | 6.302ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 7.000s | 32.230us | 50 | 50 | 100.00 | ||
| spi_host_event | 23.833m | 38.905ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.333m | 10.001ms | 35 | 50 | 70.00 |
| V2 | speed | spi_host_speed | 11.333m | 10.001ms | 35 | 50 | 70.00 |
| V2 | chip_select_timing | spi_host_speed | 11.333m | 10.001ms | 35 | 50 | 70.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.633m | 15.002ms | 36 | 50 | 72.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 1.008ms | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.333m | 10.001ms | 35 | 50 | 70.00 |
| V2 | full_cycle | spi_host_speed | 11.333m | 10.001ms | 35 | 50 | 70.00 |
| V2 | duplex | spi_host_smoke | 9.317m | 15.001ms | 43 | 50 | 86.00 |
| V2 | tx_rx_only | spi_host_smoke | 9.317m | 15.001ms | 43 | 50 | 86.00 |
| V2 | stress_all | spi_host_stress_all | 12.250m | 22.502ms | 42 | 50 | 84.00 |
| V2 | spien | spi_host_spien | 11.417m | 10.001ms | 36 | 50 | 72.00 |
| V2 | stall | spi_host_status_stall | 7.517m | 10.001ms | 37 | 50 | 74.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 10.483m | 15.002ms | 41 | 50 | 82.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.383m | 6.302ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 14.000s | 32.312us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 12.000s | 42.054us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 18.000s | 64.933us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 18.000s | 64.933us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 108.412us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 21.894us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 22.149us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 32.501us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 108.412us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 21.894us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 22.149us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 32.501us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 617 | 690 | 89.42 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 7.000s | 194.316us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 2.000s | 613.203us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 7.000s | 194.316us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 57.250m | 100.001ms | 3 | 10 | 30.00 | |
| TOTAL | 753 | 840 | 89.64 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.02 | 90.92 | 83.18 | 92.77 | 89.92 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 34 failures:
0.spi_host_speed.65554234822106379598174514879641033737850104812557244847890691176708814812136
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log
UVM_FATAL @ 10001239969 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf5c0b6d4) == 0x0
UVM_INFO @ 10001239969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_speed.63284352120117902457511760952602523262862891668598540704700634973503933259234
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_speed/latest/run.log
UVM_FATAL @ 10000818958 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa5741b94) == 0x0
UVM_INFO @ 10000818958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
0.spi_host_upper_range_clkdiv.57668339391983781528437002610424301524953064233774814441144976820591486872029
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004435843 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xebf188d4) == 0x0
UVM_INFO @ 100004435843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_upper_range_clkdiv.22709819159329755423211866143914974358921589264697532550517007753543951511043
Line 321, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100001242530 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x528b4dd4) == 0x0
UVM_INFO @ 100001242530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.spi_host_spien.42925704671997289601296766742061112637656523621654746886517135568038282487101
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 10001340092 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x93e41fd4) == 0x0
UVM_INFO @ 10001340092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_spien.44855883743882328387902986625715829438852427264520941300702870033857413113284
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_spien/latest/run.log
UVM_FATAL @ 10001003677 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x77dad3d4) == 0x0
UVM_INFO @ 10001003677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
1.spi_host_sw_reset.10359010472792152795236784478558433510035017356005401284059589745688370850093
Line 408, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10021926310 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe3b91114) == 0x0
UVM_INFO @ 10021926310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_sw_reset.27395218432885478627866214012989477496874291513290916785509338914064029141978
Line 326, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10005558169 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9af93754) == 0x0
UVM_INFO @ 10005558169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
2.spi_host_smoke.90143192240426775995162637989941235682943819830719917885749032111353289775066
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000930561 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3f6cccd4) == 0x0
UVM_INFO @ 15000930561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_smoke.80904125339706391071467100958247467516420992022088275397190199175667005204029
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
UVM_FATAL @ 15003948765 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x16cbac14) == 0x0
UVM_INFO @ 15003948765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 16 failures:
Test spi_host_status_stall has 6 failures.
1.spi_host_status_stall.63376361081414953988049656879897735765780805154607211791049555744598386707453
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10001627587 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x726c55d4) == 0x1
UVM_INFO @ 10001627587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_status_stall.38712957854398590098539214018068729400025302191922881611165030961602164137097
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003253693 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x34f03094) == 0x1
UVM_INFO @ 10003253693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_speed has 2 failures.
4.spi_host_speed.43963529450417335517755136899001351525661979332288408748517965096120057143199
Line 401, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_speed/latest/run.log
UVM_FATAL @ 10053214043 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4fa4e614) == 0x1
UVM_INFO @ 10053214043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.spi_host_speed.58043607468942167281443403124770345138993718755545001544503214217976586333332
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_speed/latest/run.log
UVM_FATAL @ 10533728100 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2e58e194) == 0x1
UVM_INFO @ 10533728100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 5 failures.
7.spi_host_spien.58481116823180214988811582712852184656245404263469754143036238115402384718910
Line 413, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_spien/latest/run.log
UVM_FATAL @ 17268709045 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc393a814) == 0x1
UVM_INFO @ 17268709045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_host_spien.72370511208293161966648110862202513193989117988887743129317617990033243010291
Line 431, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_spien/latest/run.log
UVM_FATAL @ 10284884179 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4145cb14) == 0x1
UVM_INFO @ 10284884179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_sw_reset has 2 failures.
34.spi_host_sw_reset.87637532647393186708844897930244636261216014797447886786653630629446025325167
Line 346, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15001524514 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2a9b7e14) == 0x1
UVM_INFO @ 15001524514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.spi_host_sw_reset.7197133855791157601020430053058002327999891948187946016625579008716546313489
Line 423, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15709550086 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xdaa6b9d4) == 0x1
UVM_INFO @ 15709550086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
41.spi_host_stress_all.46038703527894725368561213136953778391097146370677787814745795591171381878197
Line 420, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_stress_all/latest/run.log
UVM_FATAL @ 23033494587 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcc027a54) == 0x1
UVM_INFO @ 23033494587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 13 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
5.spi_host_upper_range_clkdiv.102652704350819537159651489802705738977503720218766455615740977002299543229912
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004254489 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x534d4214) == 0x0
UVM_INFO @ 100004254489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_upper_range_clkdiv.30538545949278798538007828959864314474875960858755526426015961131513913549121
Line 337, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002963328 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc7365b94) == 0x0
UVM_INFO @ 100002963328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 2 failures.
13.spi_host_stress_all.46515917986962445714029596016202950982434501758466375358794543878771030884106
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15004393283 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf978f14) == 0x0
UVM_INFO @ 15004393283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_stress_all.84731964670811805716558936443680279396894598713931724185574683329068786254868
Line 427, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15060226761 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x356f7654) == 0x0
UVM_INFO @ 15060226761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
14.spi_host_smoke.70368548694200810794596210946987380402776494829879128098622424572420956667105
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_smoke/latest/run.log
UVM_FATAL @ 15004543948 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x818b1154) == 0x0
UVM_INFO @ 15004543948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 8 failures.
24.spi_host_speed.79241078500142431516458828765288062489811878940030368764152317290533672524648
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_speed/latest/run.log
UVM_FATAL @ 10003758813 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x26b4e494) == 0x0
UVM_INFO @ 10003758813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_speed.36682936414515266501585649841861810454243763454881753079059907645146238153423
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_speed/latest/run.log
UVM_FATAL @ 10000745708 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6f033614) == 0x0
UVM_INFO @ 10000745708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 11 failures:
Test spi_host_spien has 1 failures.
5.spi_host_spien.42660917614182202517272187377223928596946702163824952642784699956369858608209
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_spien/latest/run.log
UVM_FATAL @ 10028305494 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xba14efd4) == 0x1
UVM_INFO @ 10028305494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 2 failures.
7.spi_host_smoke.57724692896431530436623072257316980843179283513125178136523729630961480371901
Line 455, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_smoke/latest/run.log
UVM_FATAL @ 19851684157 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7f7dfad4) == 0x1
UVM_INFO @ 19851684157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_smoke.75240883812100871086131592476097461157426514117558506166696620660311739097934
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_smoke/latest/run.log
UVM_FATAL @ 15150657191 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xff2307d4) == 0x1
UVM_INFO @ 15150657191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 5 failures.
11.spi_host_status_stall.60381141584236691427855244134950819551386468880247370907597240328041493671723
Line 913, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10610165965 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6b7fbdd4) == 0x1
UVM_INFO @ 10610165965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_host_status_stall.56781112738012858754686817946883058651241320612679129014338751144492326263129
Line 951, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10275758128 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7c6357d4) == 0x1
UVM_INFO @ 10275758128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_stress_all has 1 failures.
21.spi_host_stress_all.71975325526641516072430448349243878643363777143368699249722364466924666267031
Line 385, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10019881782 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x994d5254) == 0x1
UVM_INFO @ 10019881782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 2 failures.
23.spi_host_sw_reset.13663080764615497938994354684860046423145329145504991335492873997949010420832
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10005768711 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x178d5bd4) == 0x1
UVM_INFO @ 10005768711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_host_sw_reset.95043659742146593218355138983827921716214167966682576045406655084982025822388
Line 378, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15057195060 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3c9c9354) == 0x1
UVM_INFO @ 15057195060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 6 failures:
3.spi_host_idlecsbactive.44948709664114142161082658885846705584966987982454203873325296565765156478280
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10007978168 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd11288d4) == 0x0
UVM_INFO @ 10007978168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_idlecsbactive.89191380680598939960179043527849296159692847276339297893959860693846234392071
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15020478027 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7a2ad614) == 0x0
UVM_INFO @ 15020478027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
3.spi_host_upper_range_clkdiv.37575419594785252485653895123931211180291310471116934448366602862597886734156
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:3c485189-55cd-4d02-b30a-9688b07632c3
7.spi_host_upper_range_clkdiv.37402370054954619526815085573618601186184733523126134040888404257413232085536
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:82a8cd3b-78fc-4f05-8350-98cf4dc8524a
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
10.spi_host_idlecsbactive.10270579172362826160466369459920386307258837919025232249590351087517993911984
Line 407, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_host_idlecsbactive.58977536958743056191934122129463058756595643639194173409677086399140671458141
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:
25.spi_host_status_stall.56115058050063690203489953398753967893125878687723965867147175903475469165703
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_status_stall/latest/run.log
UVM_ERROR @ 1374212 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1374212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_status_stall.41625455144455444693833051942163281416592587101706504664903608960694122791024
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log
UVM_ERROR @ 5131437 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5131437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 1 failures:
23.spi_host_idlecsbactive.110107440047824653339447291829762953590569060616626988163786543857817469240441
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15053612550 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x71d3c194) == 0x0
UVM_INFO @ 15053612550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---