edf2fd5092| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 16.583m | 15.001ms | 40 | 50 | 80.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 26.646us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 15.293us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 170.569us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 5.000s | 96.115us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 60.871us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 15.293us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 5.000s | 96.115us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 16.364us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 62.972us | 5 | 5 | 100.00 |
| V1 | TOTAL | 105 | 115 | 91.30 | |||
| V2 | performance | spi_host_performance | 9.000s | 31.286us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.483m | 18.394ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 7.000s | 69.380us | 50 | 50 | 100.00 | ||
| spi_host_event | 15.000m | 82.944ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 7.483m | 10.011ms | 40 | 50 | 80.00 |
| V2 | speed | spi_host_speed | 7.483m | 10.011ms | 40 | 50 | 80.00 |
| V2 | chip_select_timing | spi_host_speed | 7.483m | 10.011ms | 40 | 50 | 80.00 |
| V2 | sw_reset | spi_host_sw_reset | 9.517m | 15.017ms | 38 | 50 | 76.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 11.000s | 261.294us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 7.483m | 10.011ms | 40 | 50 | 80.00 |
| V2 | full_cycle | spi_host_speed | 7.483m | 10.011ms | 40 | 50 | 80.00 |
| V2 | duplex | spi_host_smoke | 16.583m | 15.001ms | 40 | 50 | 80.00 |
| V2 | tx_rx_only | spi_host_smoke | 16.583m | 15.001ms | 40 | 50 | 80.00 |
| V2 | stress_all | spi_host_stress_all | 21.517m | 23.104ms | 39 | 50 | 78.00 |
| V2 | spien | spi_host_spien | 11.167m | 15.001ms | 40 | 50 | 80.00 |
| V2 | stall | spi_host_status_stall | 5.750m | 8.005ms | 36 | 50 | 72.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 8.133m | 15.004ms | 39 | 50 | 78.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 3.483m | 18.394ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 12.000s | 16.069us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 4.000s | 39.549us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 4.000s | 740.484us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 4.000s | 740.484us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 26.646us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 15.293us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5.000s | 96.115us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 57.496us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 26.646us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 15.293us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5.000s | 96.115us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 57.496us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 622 | 690 | 90.14 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 5.000s | 101.432us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 44.835us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 5.000s | 101.432us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 58.800m | 127.154ms | 2 | 10 | 20.00 | |
| TOTAL | 754 | 840 | 89.76 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.00 | 90.92 | 83.18 | 92.77 | 89.77 | 95.70 | 100.00 | 95.07 | 90.46 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 30 failures:
0.spi_host_upper_range_clkdiv.70463018998973203007161783242243213390045682029601284572872932129783717496871
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100000739978 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd9ba1394) == 0x0
UVM_INFO @ 100000739978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_upper_range_clkdiv.96515841976953336412702290375554179043852364724051538018020794905651774439156
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100007561979 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xde8281d4) == 0x0
UVM_INFO @ 100007561979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
1.spi_host_stress_all.68901669695890023024922079965119558281466020327118789642419036678262781839233
Line 378, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22507567514 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdfc8d7d4) == 0x0
UVM_INFO @ 22507567514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_stress_all.70439358797599520518715197842087627902190601751916005464730787511621783081782
Line 415, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15013087545 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xea381314) == 0x0
UVM_INFO @ 15013087545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
10.spi_host_speed.43691814246833328196878351272224185885510306188407220612452072099315820155315
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_speed/latest/run.log
UVM_FATAL @ 10000699456 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa52bb9d4) == 0x0
UVM_INFO @ 10000699456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_speed.12250846826383090145032594770814241779899007088618573955994002081661007565666
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_speed/latest/run.log
UVM_FATAL @ 10004560749 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4f81814) == 0x0
UVM_INFO @ 10004560749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
19.spi_host_sw_reset.21560439551625675470165546389773076310339363522281699166035512678725434603697
Line 424, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10017572362 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8d23dd94) == 0x0
UVM_INFO @ 10017572362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_sw_reset.43102047014094307648545018340316183147316946045680591036838491067550526371600
Line 316, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10019070712 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x33f6ae94) == 0x0
UVM_INFO @ 10019070712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
23.spi_host_spien.10625951422847608960379400442018564222355128199539995159530311979695506455975
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_spien/latest/run.log
UVM_FATAL @ 15001383973 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf4a59054) == 0x0
UVM_INFO @ 15001383973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.spi_host_spien.90025766756062824108973897847415751821414992543029981163920747726756454343200
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_spien/latest/run.log
UVM_FATAL @ 10001017469 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2f8be014) == 0x0
UVM_INFO @ 10001017469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 19 failures:
Test spi_host_status_stall has 9 failures.
3.spi_host_status_stall.104012921254504633038104864022649729126288717075526039228405207155139764393882
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10012861029 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x37e518d4) == 0x1
UVM_INFO @ 10012861029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_status_stall.57177593436058080150594415732432859650887449555540818046987157935118024857243
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10022441183 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb702b14) == 0x1
UVM_INFO @ 10022441183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test spi_host_speed has 4 failures.
6.spi_host_speed.79079817508744191914944275527442755761178644901307148894103069592016338335713
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/latest/run.log
UVM_FATAL @ 10037920730 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x70bdf714) == 0x1
UVM_INFO @ 10037920730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_speed.86215146437982569205070556691274575951424945575658888676104190987479965162843
Line 379, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_speed/latest/run.log
UVM_FATAL @ 10015225573 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4047ff94) == 0x1
UVM_INFO @ 10015225573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_sw_reset has 3 failures.
6.spi_host_sw_reset.36074592145817548745786208200545633091671556117166416142617013472971118220288
Line 346, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10042769017 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa6269614) == 0x1
UVM_INFO @ 10042769017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_sw_reset.7306969326863823925988063802436102304397865308685081803843089384396587705517
Line 364, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10017604750 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6499cd4) == 0x1
UVM_INFO @ 10017604750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_smoke has 2 failures.
15.spi_host_smoke.106101954883373988149590813220848270395378338345595776656460310318528924668823
Line 367, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_smoke/latest/run.log
UVM_FATAL @ 15124169128 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x368bdd94) == 0x1
UVM_INFO @ 15124169128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.spi_host_smoke.34301683191772108889365370214365453459510338083893695367743345423152176584588
Line 367, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_smoke/latest/run.log
UVM_FATAL @ 15392834683 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xeaa892d4) == 0x1
UVM_INFO @ 15392834683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
36.spi_host_spien.30257993259386435396530032333704317609394752525969574734573095274433796796097
Line 515, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_spien/latest/run.log
UVM_FATAL @ 10213159971 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x844515d4) == 0x1
UVM_INFO @ 10213159971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 17 failures:
2.spi_host_stress_all.70676208669617800247635185766150968642276333483365920062456685118300760393462
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10001542270 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xaa0facd4) == 0x0
UVM_INFO @ 10001542270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_stress_all.486747904551458415582485952253432518896252032433637722965573225129324978801
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15004769508 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x54951d14) == 0x0
UVM_INFO @ 15004769508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
2.spi_host_spien.98260505369677288359422825828812007688008583416739349478777216728896706953109
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_spien/latest/run.log
UVM_FATAL @ 10002890731 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x93928694) == 0x0
UVM_INFO @ 10002890731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_spien.4352604845140615446530716487455160036279132849848170443593739076549045834056
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_spien/latest/run.log
UVM_FATAL @ 10006203555 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfd17c054) == 0x0
UVM_INFO @ 10006203555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
3.spi_host_smoke.14299386053403025786441808121204399334320190380338579178505127808789687468702
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000682304 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf2e13c54) == 0x0
UVM_INFO @ 15000682304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_smoke.114182787773528331800535713885472864177969170487410758039910241950928875141859
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
UVM_FATAL @ 10001097693 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x672ed814) == 0x0
UVM_INFO @ 10001097693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
3.spi_host_upper_range_clkdiv.13988568669571201976620702085305116363428052901800710705518960271966411703051
Line 321, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003943745 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x615e6594) == 0x0
UVM_INFO @ 100003943745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_upper_range_clkdiv.115228317055896970623145020398813709809132905050340876666893629212878570304245
Line 329, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003323566 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x390bdb94) == 0x0
UVM_INFO @ 100003323566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 9 failures:
1.spi_host_idlecsbactive.40544075494818218665277585386113756000630488265881030950164147312203660716282
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10005044935 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3eb1e5d4) == 0x0
UVM_INFO @ 10005044935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_idlecsbactive.76224126961020051354378169347144956660000979778306971034922450844876826491844
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10017061905 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x719354) == 0x0
UVM_INFO @ 10017061905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 7 failures:
Test spi_host_sw_reset has 2 failures.
7.spi_host_sw_reset.31630514173430585544716108735651238297760715253217463524881122324199735283511
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001583437 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6a9b8314) == 0x1
UVM_INFO @ 10001583437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.spi_host_sw_reset.114215656831094225619797454332434992142181430024801018891784598605552401844460
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001702884 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x518db414) == 0x1
UVM_INFO @ 10001702884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 4 failures.
7.spi_host_status_stall.38957240059500967354290936891843111819647653429599944488345904635717667774599
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003127672 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x20bdc4d4) == 0x1
UVM_INFO @ 10003127672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.spi_host_status_stall.98713601525838950053574309634661973783324691259217567659554071760371627834456
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10015942102 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6026ec54) == 0x1
UVM_INFO @ 10015942102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_speed has 1 failures.
23.spi_host_speed.114514501083521748053570248617455510393222289151995554007549404196571469611399
Line 387, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_speed/latest/run.log
UVM_FATAL @ 10200123220 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x545087d4) == 0x1
UVM_INFO @ 10200123220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
19.spi_host_idlecsbactive.1773343458142779977062836725218150057712791632833274928651801812111331266288
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10023729424 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3a2774d4) == 0x0
UVM_INFO @ 10023729424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.spi_host_idlecsbactive.56365888703944353194685558411840939639341675225613571138978599769923886599697
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15003634208 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb4c74854) == 0x0
UVM_INFO @ 15003634208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:
1.spi_host_status_stall.46377684241107143120701499403509734089005564233902456257283119543991860427798
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_ERROR @ 2848051 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2848051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
4.spi_host_upper_range_clkdiv.76399699403592877811021913547219441793432921671124787145845369090981617483860
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:200b0124-82b1-4aca-9e69-75ea1c061936