SPI_HOST Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 16.433m 15.001ms 45 50 90.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 16.570us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 35.104us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 648.160us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 54.168us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 61.975us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 35.104us 20 20 100.00
spi_host_csr_aliasing 3.000s 54.168us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 16.526us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 52.121us 5 5 100.00
V1 TOTAL 110 115 95.65
V2 performance spi_host_performance 4.000s 92.054us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 1.750m 2.431ms 50 50 100.00
spi_host_error_cmd 3.000s 20.053us 50 50 100.00
spi_host_event 18.983m 95.890ms 50 50 100.00
V2 clock_rate spi_host_speed 5.817m 10.001ms 41 50 82.00
V2 speed spi_host_speed 5.817m 10.001ms 41 50 82.00
V2 chip_select_timing spi_host_speed 5.817m 10.001ms 41 50 82.00
V2 sw_reset spi_host_sw_reset 10.283m 15.001ms 30 50 60.00
V2 passthrough_mode spi_host_passthrough_mode 3.000s 250.803us 50 50 100.00
V2 cpol_cpha spi_host_speed 5.817m 10.001ms 41 50 82.00
V2 full_cycle spi_host_speed 5.817m 10.001ms 41 50 82.00
V2 duplex spi_host_smoke 16.433m 15.001ms 45 50 90.00
V2 tx_rx_only spi_host_smoke 16.433m 15.001ms 45 50 90.00
V2 stress_all spi_host_stress_all 15.583m 15.002ms 37 50 74.00
V2 spien spi_host_spien 16.433m 15.001ms 33 50 66.00
V2 stall spi_host_status_stall 10.533m 15.001ms 33 50 66.00
V2 Idlecsbactive spi_host_idlecsbactive 11.450m 200.000ms 39 50 78.00
V2 data_fifo_status spi_host_overflow_underflow 1.750m 2.431ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 22.090us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 28.468us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 4.000s 343.461us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 4.000s 343.461us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 16.570us 5 5 100.00
spi_host_csr_rw 3.000s 35.104us 20 20 100.00
spi_host_csr_aliasing 3.000s 54.168us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 23.157us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 16.570us 5 5 100.00
spi_host_csr_rw 3.000s 35.104us 20 20 100.00
spi_host_csr_aliasing 3.000s 54.168us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 23.157us 20 20 100.00
V2 TOTAL 603 690 87.39
V2S tl_intg_err spi_host_tl_intg_err 3.000s 147.616us 20 20 100.00
spi_host_sec_cm 2.000s 39.021us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 3.000s 147.616us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 55.667m 100.001ms 2 10 20.00
TOTAL 740 840 88.10

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.02 90.92 83.18 92.77 89.92 95.70 100.00 95.07 90.87

Failure Buckets

Past Results