5967df933a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 16.433m | 15.001ms | 45 | 50 | 90.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 16.570us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 35.104us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 648.160us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 54.168us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 61.975us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 35.104us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 54.168us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 16.526us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 52.121us | 5 | 5 | 100.00 |
| V1 | TOTAL | 110 | 115 | 95.65 | |||
| V2 | performance | spi_host_performance | 4.000s | 92.054us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 1.750m | 2.431ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 20.053us | 50 | 50 | 100.00 | ||
| spi_host_event | 18.983m | 95.890ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.817m | 10.001ms | 41 | 50 | 82.00 |
| V2 | speed | spi_host_speed | 5.817m | 10.001ms | 41 | 50 | 82.00 |
| V2 | chip_select_timing | spi_host_speed | 5.817m | 10.001ms | 41 | 50 | 82.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.283m | 15.001ms | 30 | 50 | 60.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 250.803us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.817m | 10.001ms | 41 | 50 | 82.00 |
| V2 | full_cycle | spi_host_speed | 5.817m | 10.001ms | 41 | 50 | 82.00 |
| V2 | duplex | spi_host_smoke | 16.433m | 15.001ms | 45 | 50 | 90.00 |
| V2 | tx_rx_only | spi_host_smoke | 16.433m | 15.001ms | 45 | 50 | 90.00 |
| V2 | stress_all | spi_host_stress_all | 15.583m | 15.002ms | 37 | 50 | 74.00 |
| V2 | spien | spi_host_spien | 16.433m | 15.001ms | 33 | 50 | 66.00 |
| V2 | stall | spi_host_status_stall | 10.533m | 15.001ms | 33 | 50 | 66.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 11.450m | 200.000ms | 39 | 50 | 78.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 1.750m | 2.431ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 22.090us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 28.468us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 4.000s | 343.461us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 4.000s | 343.461us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 16.570us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 35.104us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 54.168us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 23.157us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 16.570us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 35.104us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 54.168us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 23.157us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 603 | 690 | 87.39 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 147.616us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 2.000s | 39.021us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 147.616us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 55.667m | 100.001ms | 2 | 10 | 20.00 | |
| TOTAL | 740 | 840 | 88.10 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.02 | 90.92 | 83.18 | 92.77 | 89.92 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 35 failures:
Test spi_host_spien has 7 failures.
0.spi_host_spien.54550169605207438140922372000698598046655827441895670185767670112857330358409
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 10000941571 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x82c32354) == 0x0
UVM_INFO @ 10000941571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.spi_host_spien.27087843400714362350590245549074667550049111217675278355033521981765791540993
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_spien/latest/run.log
UVM_FATAL @ 10001008505 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x458646d4) == 0x0
UVM_INFO @ 10001008505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_host_upper_range_clkdiv has 2 failures.
1.spi_host_upper_range_clkdiv.100999269923279656311393437830108605072043663933439941188912520987460974679878
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100001034905 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6d925094) == 0x0
UVM_INFO @ 100001034905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_upper_range_clkdiv.62553872430212600979680014413580379198042365846787424282448699684479391424328
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003960231 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6a910f94) == 0x0
UVM_INFO @ 100003960231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 3 failures.
2.spi_host_smoke.18501383080527914994787298092762858261963056388489257051823385757222215816994
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001931874 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdf311e94) == 0x0
UVM_INFO @ 15001931874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_smoke.26321753585069184411046095509630736307035294264876455278289425021370591471218
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_smoke/latest/run.log
UVM_FATAL @ 15004063033 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x634ad854) == 0x0
UVM_INFO @ 15004063033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_speed has 4 failures.
3.spi_host_speed.31654937429313090209063362444764769090611765234846186037618129572119916532584
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_speed/latest/run.log
UVM_FATAL @ 10003073226 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xba620bd4) == 0x0
UVM_INFO @ 10003073226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_host_speed.90324726195083447483859500964437444657115010986292693946888037372112541878050
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_speed/latest/run.log
UVM_FATAL @ 10002979060 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x249eb654) == 0x0
UVM_INFO @ 10002979060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_sw_reset has 11 failures.
6.spi_host_sw_reset.44933901068489857175075537829462909019450781637334565904862357031453360769823
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002997639 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5d3b4354) == 0x0
UVM_INFO @ 10002997639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_sw_reset.23620653478737418866944439836123934999326640520170644520630148392498473228081
Line 334, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002357100 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x47216294) == 0x0
UVM_INFO @ 10002357100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
... and 2 more tests.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 20 failures:
Test spi_host_status_stall has 8 failures.
2.spi_host_status_stall.104126207697774041651855848944943533698370682646991617452571488594379904550158
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10001855761 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x88f8ca54) == 0x1
UVM_INFO @ 10001855761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_status_stall.73030862008428109153960387004707500625639710349091960342352390045269323210079
Line 415, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15911381696 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa56caa54) == 0x1
UVM_INFO @ 15911381696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test spi_host_upper_range_clkdiv has 1 failures.
9.spi_host_upper_range_clkdiv.100570438671314734177437015442230517826580838089228190980285385190825411019546
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 131606138365 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa9da5f54) == 0x1
UVM_INFO @ 131606138365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 7 failures.
11.spi_host_sw_reset.9357266372613581461798338388920720777387921462824512548975042566506390247096
Line 370, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10006174619 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa5e05454) == 0x1
UVM_INFO @ 10006174619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_sw_reset.15159003395145283449386617181358350372610224995313745069055940462184387170075
Line 370, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15003757809 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xff435214) == 0x1
UVM_INFO @ 15003757809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_host_stress_all has 1 failures.
16.spi_host_stress_all.83271072475049078351790887807162700767540219520586348935202225634059196620044
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15125617197 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7e2a2294) == 0x1
UVM_INFO @ 15125617197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
29.spi_host_speed.114293417584085514485902450576715984224294720448341749977224760215075727119701
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_speed/latest/run.log
UVM_FATAL @ 10036119648 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5a0d2c14) == 0x1
UVM_INFO @ 10036119648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 18 failures:
Test spi_host_stress_all has 5 failures.
4.spi_host_stress_all.65234711934851346425606002110678246092224172847264661980497842658199248337844
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10001263757 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1a3f6b94) == 0x0
UVM_INFO @ 10001263757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_stress_all.92263158301629898731266440252452771732832292434247365596252379588920401968389
Line 431, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15040049056 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x763fc154) == 0x0
UVM_INFO @ 15040049056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_spien has 7 failures.
6.spi_host_spien.102303851067764894208435687925240242454442983068236473214666544370481906139547
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_spien/latest/run.log
UVM_FATAL @ 10004382190 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5d14b114) == 0x0
UVM_INFO @ 10004382190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_spien.36469763024849571345169086471933408723056173409854558411319003954968645031497
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_spien/latest/run.log
UVM_FATAL @ 10000926222 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5bab05d4) == 0x0
UVM_INFO @ 10000926222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_host_upper_range_clkdiv has 1 failures.
7.spi_host_upper_range_clkdiv.57796931245446168103687595891653282780417212673731901372807844324556599131891
Line 307, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100022277680 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xeaff4714) == 0x0
UVM_INFO @ 100022277680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 2 failures.
11.spi_host_smoke.24007363718566389444291707020484155288700002147072592397492685457600543908874
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001022872 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x771b6d14) == 0x0
UVM_INFO @ 15001022872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.spi_host_smoke.102460864626131710632576788876871559875784256615741744480727890830678893682778
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_smoke/latest/run.log
UVM_FATAL @ 15004285542 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb621be54) == 0x0
UVM_INFO @ 15004285542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 2 failures.
16.spi_host_speed.18177042678596695618604932627496726370572719611128750849160882086461955251234
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_speed/latest/run.log
UVM_FATAL @ 10005341827 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb65f1614) == 0x0
UVM_INFO @ 10005341827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_speed.100167029795587323443254022932010298646429078498632655539683818899864063706563
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_speed/latest/run.log
UVM_FATAL @ 10000998971 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xee80be54) == 0x0
UVM_INFO @ 10000998971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 7 failures:
0.spi_host_idlecsbactive.69612129574627741732687591879233552042198103758246897573608405904878357983730
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004759999 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4e7c694) == 0x0
UVM_INFO @ 10004759999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_host_idlecsbactive.53892721706436493674959726564013107157349852484256858397574543131722055806898
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10003697949 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x672c8814) == 0x0
UVM_INFO @ 10003697949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
5.spi_host_upper_range_clkdiv.85966321728906749818662507595962195502493320004532704913416880376325494355628
Line 331, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003355911 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7ab1e6d4) == 0x0
UVM_INFO @ 100003355911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 7 failures:
Test spi_host_spien has 1 failures.
12.spi_host_spien.36723567691386890927746192877480946880289403889904341473256135774698614597558
Line 445, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_spien/latest/run.log
UVM_FATAL @ 10234091259 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6b99c954) == 0x1
UVM_INFO @ 10234091259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 2 failures.
31.spi_host_speed.102883066387121228609403823400896348207565913374811658391156815338992784081711
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_speed/latest/run.log
UVM_FATAL @ 10039511860 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x334fbc54) == 0x1
UVM_INFO @ 10039511860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.spi_host_speed.25077298253913952794268770786090301216829107861618019255176689467369345377426
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_speed/latest/run.log
UVM_FATAL @ 10374980355 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x57db20d4) == 0x1
UVM_INFO @ 10374980355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 3 failures.
36.spi_host_status_stall.80467538050878959404765074915946616459570829689545549400480724082300694208060
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15001478791 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc93a7c54) == 0x1
UVM_INFO @ 15001478791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.spi_host_status_stall.35050291014117475075900069470970475473809232856251582048117127011785181714457
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003614354 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x94b5ce54) == 0x1
UVM_INFO @ 10003614354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_sw_reset has 1 failures.
37.spi_host_sw_reset.68719893607614373553480137782266628665431030772810456679749277793057730288971
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10016997762 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa9844694) == 0x1
UVM_INFO @ 10016997762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
8.spi_host_idlecsbactive.88841374025437233314298854222328023692830596696070987647812483118059460119433
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10015463686 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb5836314) == 0x0
UVM_INFO @ 10015463686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_idlecsbactive.62145912831103803294965495916991511332025842288133091282661836482247545800805
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004801153 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd21dca14) == 0x0
UVM_INFO @ 10004801153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
2.spi_host_upper_range_clkdiv.9376586243748153538373847880432333454247762893283668550557466599420329485467
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:d178273c-03a6-4108-8d80-b1bff05e051b
3.spi_host_upper_range_clkdiv.31827591508323673239679285649661730973229888509658482479146058811656751895864
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:adc39c67-82fe-4394-a8a8-fe2120fed396
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 3 failures:
13.spi_host_status_stall.19502549807463562665313727000392795511194583416077490956085087524523489519655
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
UVM_ERROR @ 3814257 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 3814257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.spi_host_status_stall.78145337816057869588111514104287989864883686821833620880151492401212627119116
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_status_stall/latest/run.log
UVM_ERROR @ 14357519 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 14357519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:
1.spi_host_status_stall.19837038409778193951008008030104916599704473238029794347065151337054934457438
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_ERROR @ 14105032 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 14105032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.spi_host_status_stall.84284025514811192103257484382040541786754484140044871990384096625285153597242
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_status_stall/latest/run.log
UVM_ERROR @ 16629445 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 16629445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
46.spi_host_idlecsbactive.11876055583341157029509738048519826665213237130200579439905383714613208358768
Line 407, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---