d51405297e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 17.000m | 15.001ms | 33 | 50 | 66.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 47.962us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 18.310us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 4.000s | 58.276us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 19.660us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 35.117us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 18.310us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 19.660us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 70.181us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 2.000s | 25.621us | 5 | 5 | 100.00 |
| V1 | TOTAL | 98 | 115 | 85.22 | |||
| V2 | performance | spi_host_performance | 3.000s | 113.834us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.150m | 5.868ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 16.289us | 50 | 50 | 100.00 | ||
| spi_host_event | 7.767m | 31.839ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.000m | 10.001ms | 43 | 50 | 86.00 |
| V2 | speed | spi_host_speed | 11.000m | 10.001ms | 43 | 50 | 86.00 |
| V2 | chip_select_timing | spi_host_speed | 11.000m | 10.001ms | 43 | 50 | 86.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.050m | 15.548ms | 40 | 50 | 80.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 535.539us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.000m | 10.001ms | 43 | 50 | 86.00 |
| V2 | full_cycle | spi_host_speed | 11.000m | 10.001ms | 43 | 50 | 86.00 |
| V2 | duplex | spi_host_smoke | 17.000m | 15.001ms | 33 | 50 | 66.00 |
| V2 | tx_rx_only | spi_host_smoke | 17.000m | 15.001ms | 33 | 50 | 66.00 |
| V2 | stress_all | spi_host_stress_all | 17.667m | 15.013ms | 37 | 50 | 74.00 |
| V2 | spien | spi_host_spien | 18.133m | 15.001ms | 30 | 50 | 60.00 |
| V2 | stall | spi_host_status_stall | 8.233m | 10.391ms | 36 | 50 | 72.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 13.217m | 200.000ms | 39 | 50 | 78.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.150m | 5.868ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 89.149us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 41.880us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 4.000s | 82.550us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 4.000s | 82.550us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 47.962us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 18.310us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 19.660us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 100.650us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 47.962us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 18.310us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 19.660us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 100.650us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 615 | 690 | 89.13 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 82.267us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 261.097us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 82.267us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 51.200m | 100.004ms | 5 | 10 | 50.00 | |
| TOTAL | 743 | 840 | 88.45 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.77 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 42 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
0.spi_host_upper_range_clkdiv.2202139868370508571403774374591901477972241308622488922179537694313961387475
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003711262 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x50c79494) == 0x0
UVM_INFO @ 100003711262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_upper_range_clkdiv.42236912312330706109879612187706147848423327351767940761245286478411762022123
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100010850369 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x63451554) == 0x0
UVM_INFO @ 100010850369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 14 failures.
0.spi_host_spien.66632931928807185754549360552228752273367211412905841305230775967289769339996
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 10001257520 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbd4c3854) == 0x0
UVM_INFO @ 10001257520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_spien.53483214357239377181849613932648612470343571008952174204052749820067319291194
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_spien/latest/run.log
UVM_FATAL @ 10006014910 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe74bee14) == 0x0
UVM_INFO @ 10006014910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Test spi_host_sw_reset has 6 failures.
3.spi_host_sw_reset.39213958148047278523497676691660029230114065242855542550717894216186665937685
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003109442 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x68fde814) == 0x0
UVM_INFO @ 10003109442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.spi_host_sw_reset.38195818683693238902582585735604498241174102104860404627739836845710759082967
Line 379, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15548420960 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x281ad414) == 0x0
UVM_INFO @ 15548420960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_stress_all has 8 failures.
4.spi_host_stress_all.14370919322026901878516406772091845321103198081843617502485751206806053782870
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10000689596 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x88e36e54) == 0x0
UVM_INFO @ 10000689596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.spi_host_stress_all.106391835718777585063684874937702811979468694852678281012235873460546182505661
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15002090630 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc70995d4) == 0x0
UVM_INFO @ 15002090630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test spi_host_smoke has 8 failures.
5.spi_host_smoke.46253880345014813592740180678647843218683691355788213738310891115398418432165
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001008687 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf96eb194) == 0x0
UVM_INFO @ 15001008687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_smoke.54509762681378880745544970226408318283075360785116882763251483939235085312647
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001075000 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa90bfa14) == 0x0
UVM_INFO @ 15001075000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
... and 1 more tests.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 17 failures:
Test spi_host_status_stall has 10 failures.
1.spi_host_status_stall.25402273966676356210582897694324171883366679639031672134064802543113279674187
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10007028078 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa0bd1154) == 0x1
UVM_INFO @ 10007028078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_status_stall.40829757188861212529343276951272015096540510872091116347585778510321047110754
Line 937, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log
UVM_FATAL @ 12295815995 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x675223d4) == 0x1
UVM_INFO @ 12295815995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test spi_host_spien has 2 failures.
2.spi_host_spien.28464799390421070163220020520241925448198271992879185437155946536892720373837
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_spien/latest/run.log
UVM_FATAL @ 15522596693 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcc0346d4) == 0x1
UVM_INFO @ 15522596693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.spi_host_spien.90201846153915368243527239616391702225050383522651445244574844044774299455947
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_spien/latest/run.log
UVM_FATAL @ 10007696926 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb99b1954) == 0x1
UVM_INFO @ 10007696926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 2 failures.
6.spi_host_sw_reset.37897098955759420900379717195614298358044922415687453395021733681405937254004
Line 374, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10014876568 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa0433294) == 0x1
UVM_INFO @ 10014876568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_sw_reset.49812863479191549692389749741173481968289994667472599688408752891793343900237
Line 449, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10029428409 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd57bcbd4) == 0x1
UVM_INFO @ 10029428409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 2 failures.
9.spi_host_smoke.16812643403462649163361482930571086459603960806868183624452054655494993687354
Line 371, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_smoke/latest/run.log
UVM_FATAL @ 10010187258 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x16d566d4) == 0x1
UVM_INFO @ 10010187258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.spi_host_smoke.114194784032352718309607643413226140690361226160928782637579221929207034269378
Line 439, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_smoke/latest/run.log
UVM_FATAL @ 15468275318 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x75b638d4) == 0x1
UVM_INFO @ 15468275318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
30.spi_host_speed.90960493953762071076605424919136381891224196829371495261781760299864544131586
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_speed/latest/run.log
UVM_FATAL @ 10006852308 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x180af914) == 0x1
UVM_INFO @ 10006852308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 15 failures:
Test spi_host_smoke has 5 failures.
3.spi_host_smoke.37899215655854002133483193940927509955404493548832904765761238318106154305035
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_smoke/latest/run.log
UVM_FATAL @ 10001999637 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3ac1c7d4) == 0x0
UVM_INFO @ 10001999637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_smoke.102825071331038254802017011107763364595836215634424519614828460790911791314013
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001897016 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x64724d4) == 0x0
UVM_INFO @ 15001897016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_upper_range_clkdiv has 1 failures.
3.spi_host_upper_range_clkdiv.7877743601540497225675204855196553220837050417147361926094091878073792190196
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003781300 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5652b954) == 0x0
UVM_INFO @ 100003781300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
4.spi_host_speed.103618925036513655743519041989984135755180248679447369065252245571627401567343
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_speed/latest/run.log
UVM_FATAL @ 10009710091 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa5528c54) == 0x0
UVM_INFO @ 10009710091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 1 failures.
5.spi_host_sw_reset.65791389015654905288423990065337230683987669013841512011421897421254519164104
Line 697, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10020124417 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2dd98454) == 0x0
UVM_INFO @ 10020124417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 2 failures.
17.spi_host_spien.66331935095793244044916620443752579529685211924881361429462193192054547453938
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_spien/latest/run.log
UVM_FATAL @ 15003263117 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x93d54b14) == 0x0
UVM_INFO @ 15003263117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_host_spien.68005144977676177880341212700526787458788960000818093099537890832685670266365
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_spien/latest/run.log
UVM_FATAL @ 10002195097 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4e2e0314) == 0x0
UVM_INFO @ 10002195097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 8 failures:
Test spi_host_upper_range_clkdiv has 1 failures.
2.spi_host_upper_range_clkdiv.19849212809604583361189574047796394798295983909990856413661486265306425704446
Line 331, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002896173 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x36f332d4) == 0x0
UVM_INFO @ 100002896173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_idlecsbactive has 7 failures.
9.spi_host_idlecsbactive.25419950641616781547709189990032558835923277699046548882366971617432993768735
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10003944374 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8f5c3494) == 0x0
UVM_INFO @ 10003944374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_host_idlecsbactive.104524463780370209178355392781309074801548518363931328381829091409584507392175
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10009744648 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xce3eb894) == 0x0
UVM_INFO @ 10009744648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 7 failures:
Test spi_host_sw_reset has 1 failures.
2.spi_host_sw_reset.37891504136361721915445264821690845956940609410645527515778658021418474422689
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003995630 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x25de1c14) == 0x1
UVM_INFO @ 10003995630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
14.spi_host_speed.91983645583257863696559043062729221786935803108797553609483495250654472562158
Line 419, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_speed/latest/run.log
UVM_FATAL @ 10026359617 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x46037c54) == 0x1
UVM_INFO @ 10026359617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
33.spi_host_status_stall.19162104213614544418294502752216785147707677062000847724574372451267584832684
Line 891, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10361632116 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfd175654) == 0x1
UVM_INFO @ 10361632116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 2 failures.
37.spi_host_spien.26474405510243989612112749894772839364517494176211351117260567953185181949714
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_spien/latest/run.log
UVM_FATAL @ 10007361671 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x135c2554) == 0x1
UVM_INFO @ 10007361671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.spi_host_spien.32708532576373106912451253216360343201895569588484192602235966556421900053182
Line 493, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_spien/latest/run.log
UVM_FATAL @ 10200420608 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x41524014) == 0x1
UVM_INFO @ 10200420608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 2 failures.
48.spi_host_smoke.59348844832839932085631113464108132401843948401790783196491501663236141320956
Line 371, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_smoke/latest/run.log
UVM_FATAL @ 15037683282 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe4077614) == 0x1
UVM_INFO @ 15037683282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.spi_host_smoke.99276240133120179669399571052470071334883478748114491213222958374545296665260
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_smoke/latest/run.log
UVM_FATAL @ 19645777225 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2017cd4) == 0x1
UVM_INFO @ 19645777225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 4 failures:
Test spi_host_status_stall has 1 failures.
17.spi_host_status_stall.47125059463726893233180721491538032548903482529600020327554200976440845827218
Line 1122, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_status_stall/latest/run.log
UVM_FATAL @ 25740303415 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb9bf3794) == 0x0
UVM_INFO @ 25740303415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_idlecsbactive has 3 failures.
21.spi_host_idlecsbactive.5542845885533172351305058944335179621165652471731169880523869118686014204809
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002339242 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x95e9fcd4) == 0x0
UVM_INFO @ 10002339242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_idlecsbactive.104662346082211667429795147986928718863739059885661706251489796418942777110670
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10011630513 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb6110114) == 0x0
UVM_INFO @ 10011630513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 2 failures:
16.spi_host_status_stall.67651422105457588817781150978681834228504571568745402362331261665264109481339
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_status_stall/latest/run.log
UVM_ERROR @ 7525708 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 7525708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_host_status_stall.4294943671434444183638853116929590685150130576989156705148053754069536184600
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
UVM_ERROR @ 6468942 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 6468942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
8.spi_host_upper_range_clkdiv.90754616797579996862354295153111414489367622103961841553986570567824306040717
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:d8f182d9-a569-47ea-997f-51f0771d7634
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
28.spi_host_idlecsbactive.75050054624083041940957557168841368623916021137060251864914017456265342868707
Line 403, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---