c04cc5d074| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 11.483m | 15.262ms | 36 | 50 | 72.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 16.035us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 2.000s | 34.301us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 104.970us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 34.410us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 65.091us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 2.000s | 34.301us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 34.410us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 20.878us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 2.000s | 20.070us | 5 | 5 | 100.00 |
| V1 | TOTAL | 101 | 115 | 87.83 | |||
| V2 | performance | spi_host_performance | 13.000s | 29.543us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.717m | 31.700ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 12.000s | 18.105us | 50 | 50 | 100.00 | ||
| spi_host_event | 18.950m | 114.080ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.400m | 10.001ms | 37 | 50 | 74.00 |
| V2 | speed | spi_host_speed | 11.400m | 10.001ms | 37 | 50 | 74.00 |
| V2 | chip_select_timing | spi_host_speed | 11.400m | 10.001ms | 37 | 50 | 74.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.950m | 15.244ms | 32 | 50 | 64.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 7.000s | 135.348us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.400m | 10.001ms | 37 | 50 | 74.00 |
| V2 | full_cycle | spi_host_speed | 11.400m | 10.001ms | 37 | 50 | 74.00 |
| V2 | duplex | spi_host_smoke | 11.483m | 15.262ms | 36 | 50 | 72.00 |
| V2 | tx_rx_only | spi_host_smoke | 11.483m | 15.262ms | 36 | 50 | 72.00 |
| V2 | stress_all | spi_host_stress_all | 12.850m | 22.501ms | 41 | 50 | 82.00 |
| V2 | spien | spi_host_spien | 10.900m | 10.001ms | 41 | 50 | 82.00 |
| V2 | stall | spi_host_status_stall | 5.517m | 15.003ms | 42 | 50 | 84.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 8.600m | 200.000ms | 36 | 50 | 72.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.717m | 31.700ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 12.000s | 17.870us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 18.394us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 4.000s | 82.948us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 4.000s | 82.948us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 16.035us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 2.000s | 34.301us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 34.410us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 112.804us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 16.035us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 2.000s | 34.301us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 34.410us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 112.804us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 619 | 690 | 89.71 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 52.038us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 228.474us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 52.038us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 58.267m | 200.000ms | 1 | 10 | 10.00 | |
| TOTAL | 746 | 840 | 88.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.84 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 43 failures:
1.spi_host_speed.56863921126700799186055351658189207883450836168205182111752742391910225538015
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_speed/latest/run.log
UVM_FATAL @ 10004533344 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xeeaa2f94) == 0x0
UVM_INFO @ 10004533344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_speed.62631735458364265591888080778195984918750576368675305045355473572704510140521
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_speed/latest/run.log
UVM_FATAL @ 10001030413 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x32367d54) == 0x0
UVM_INFO @ 10001030413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
2.spi_host_upper_range_clkdiv.3826439589324942478268488840635087359051343837857706650718373047682850332833
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003033411 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe79e41d4) == 0x0
UVM_INFO @ 100003033411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_upper_range_clkdiv.69483728884480957709657783806851505808505804901590038386973593013285186036140
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002042313 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x401f7794) == 0x0
UVM_INFO @ 100002042313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
3.spi_host_smoke.3881016972085903991986789107369886744346972692424781571911964970996988925163
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_smoke/latest/run.log
UVM_FATAL @ 15003128968 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc4233ad4) == 0x0
UVM_INFO @ 15003128968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_smoke.89460109732402355704186755630913815396529140509049984558219584160083398116975
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_smoke/latest/run.log
UVM_FATAL @ 15009440680 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x67445354) == 0x0
UVM_INFO @ 15009440680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
3.spi_host_stress_all.106328240313286172893256983514744560169850401832857504189263692119923167331018
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22501184894 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4fa100d4) == 0x0
UVM_INFO @ 22501184894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_stress_all.49221697292126667452520882153214907806291836883145717830463550421274608251269
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001364684 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9a923a54) == 0x0
UVM_INFO @ 15001364684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
5.spi_host_spien.18579153070655943664046918865243462636976297638794167119568623456580901735154
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_spien/latest/run.log
UVM_FATAL @ 10003487404 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x89dd86d4) == 0x0
UVM_INFO @ 10003487404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_spien.64523997646178526376172413050335789337074160716702532835814376978469325356431
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_spien/latest/run.log
UVM_FATAL @ 10001367483 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x13b83c94) == 0x0
UVM_INFO @ 10001367483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 17 failures:
Test spi_host_status_stall has 3 failures.
2.spi_host_status_stall.50762654644323045230902629136017735678881684961408982580452763654240609035857
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003214525 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7a4bcb14) == 0x1
UVM_INFO @ 10003214525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_status_stall.45764485737634656565967068204122278006506332756690590343036712297552619634243
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15002881838 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4d8d4194) == 0x1
UVM_INFO @ 15002881838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_spien has 2 failures.
2.spi_host_spien.2710966347173041531148537874185039954143488721163497786087785041995018912990
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_spien/latest/run.log
UVM_FATAL @ 10013555027 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7e617114) == 0x1
UVM_INFO @ 10013555027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_host_spien.112379164495872127074512017668178453737691911656287122578918869852240694122640
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_spien/latest/run.log
UVM_FATAL @ 15727105697 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5a6c3294) == 0x1
UVM_INFO @ 15727105697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 7 failures.
3.spi_host_sw_reset.110319829732073391518917463968283961622002625495187627036605242808703885317447
Line 459, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10025198714 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb9605814) == 0x1
UVM_INFO @ 10025198714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_host_sw_reset.59721401271005718091846836506490960728704991196752272042193538792822334874916
Line 474, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10058473293 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xbdcb8454) == 0x1
UVM_INFO @ 10058473293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_host_smoke has 3 failures.
24.spi_host_smoke.89597420030064187589101400530815889207637224156775953411742364444515089082034
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_smoke/latest/run.log
UVM_FATAL @ 15262086284 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x63931914) == 0x1
UVM_INFO @ 15262086284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_smoke.71713058586659692030686011242424573678154252672573321565073623520728350346403
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_smoke/latest/run.log
UVM_FATAL @ 15240387644 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcf12094) == 0x1
UVM_INFO @ 15240387644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_speed has 2 failures.
32.spi_host_speed.35515512439354869220315344717633667052305426010177389559435626389537913736337
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_speed/latest/run.log
UVM_FATAL @ 10047045922 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x92ea3854) == 0x1
UVM_INFO @ 10047045922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_host_speed.57401130797057984619930781315573729244285210363418765230346685356847386849729
Line 489, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_speed/latest/run.log
UVM_FATAL @ 11184509003 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xff59f194) == 0x1
UVM_INFO @ 11184509003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 8 failures:
4.spi_host_idlecsbactive.19474569987824583203941898645557976170217433937165677988126623568693276953185
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10010162376 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa0613d54) == 0x0
UVM_INFO @ 10010162376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_idlecsbactive.110990816547314263845739118196995068760255027712404348744039615737857681351850
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004375956 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3fb4bc14) == 0x0
UVM_INFO @ 10004375956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 8 failures:
Test spi_host_stress_all has 3 failures.
4.spi_host_stress_all.11699826449170763495366728638844051292423566123788857370171604743940770201281
Line 426, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15033313137 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2c62b594) == 0x0
UVM_INFO @ 15033313137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_stress_all.78636627317902213584145253268648100370685712391984303341147236644190784878924
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15020185441 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf2498494) == 0x0
UVM_INFO @ 15020185441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_speed has 3 failures.
13.spi_host_speed.19507260207367480676686892077243389099001691676286866736876887384297004788106
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_speed/latest/run.log
UVM_FATAL @ 10000809975 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd3dce594) == 0x0
UVM_INFO @ 10000809975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_speed.104019023745259082711796281713790820115837022955814863097927307999366868590740
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_speed/latest/run.log
UVM_FATAL @ 10001036997 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xefcf9954) == 0x0
UVM_INFO @ 10001036997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_spien has 1 failures.
26.spi_host_spien.75355736062543746765210945343976381441487195498905401866060200155495503428253
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_spien/latest/run.log
UVM_FATAL @ 10000985016 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7f24f754) == 0x0
UVM_INFO @ 10000985016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
27.spi_host_smoke.94800432034899462971796198453415679431097536319109868674734291958900331116389
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_smoke/latest/run.log
UVM_FATAL @ 15002835560 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x64b09694) == 0x0
UVM_INFO @ 15002835560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
0.spi_host_upper_range_clkdiv.24217586932084032504526216429251288097889027612163775918873831105872764660344
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:f1a7875d-b861-4a88-ba63-cec1a5907a65
1.spi_host_upper_range_clkdiv.103369145060414367042333201813884396751607501627902203880893938623943290781269
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:3da543b1-7728-4f4c-9189-6b77b2d21569
... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 5 failures:
1.spi_host_idlecsbactive.59713247308845815514789226008781119467202091760755128652672645364865660502072
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10003520099 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe02cc994) == 0x0
UVM_INFO @ 10003520099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.spi_host_idlecsbactive.63100891594173363616653084260838249139668882060216953058409274471927436756822
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15013856526 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3fa7dd4) == 0x0
UVM_INFO @ 15013856526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 3 failures:
22.spi_host_status_stall.92686721196802687864087335141157013797578161664354628114205911830767680851855
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
UVM_ERROR @ 7611830 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 7611830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_host_status_stall.87058847686049844309254732590063780977812661193583269113433779752891900973510
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
UVM_ERROR @ 5116306 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 5116306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
Test spi_host_status_stall has 1 failures.
4.spi_host_status_stall.82148346238621068149674851837775206199487727291887816223953335380575813385039
Line 963, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log
UVM_FATAL @ 14377795862 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5746e254) == 0x1
UVM_INFO @ 14377795862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
48.spi_host_speed.100891459969923222887747776880678670887134743897608268825640993527713934240252
Line 393, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_speed/latest/run.log
UVM_FATAL @ 10091575146 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6a806cd4) == 0x1
UVM_INFO @ 10091575146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test spi_host_upper_range_clkdiv has 1 failures.
6.spi_host_upper_range_clkdiv.107106498237547575466479923329775391767520068369294533000285984216904203820339
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_idlecsbactive has 1 failures.
18.spi_host_idlecsbactive.49478815468406074051643334768892676413134414127282889337538701899279550275992
Line 395, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:
46.spi_host_status_stall.2700760928273578102522260737037382247464730835528452013795931869884508387407
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_status_stall/latest/run.log
UVM_ERROR @ 6072862 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6072862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---