a04e34f557| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 17.067m | 15.001ms | 36 | 50 | 72.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 18.291us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 44.552us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 132.988us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 2.000s | 158.398us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 138.406us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 44.552us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 2.000s | 158.398us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 51.190us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 55.307us | 5 | 5 | 100.00 |
| V1 | TOTAL | 101 | 115 | 87.83 | |||
| V2 | performance | spi_host_performance | 3.000s | 54.392us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.850m | 10.349ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 20.926us | 50 | 50 | 100.00 | ||
| spi_host_event | 2.517m | 89.986ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.717m | 10.001ms | 38 | 50 | 76.00 |
| V2 | speed | spi_host_speed | 11.717m | 10.001ms | 38 | 50 | 76.00 |
| V2 | chip_select_timing | spi_host_speed | 11.717m | 10.001ms | 38 | 50 | 76.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.933m | 15.002ms | 43 | 50 | 86.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 457.396us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.717m | 10.001ms | 38 | 50 | 76.00 |
| V2 | full_cycle | spi_host_speed | 11.717m | 10.001ms | 38 | 50 | 76.00 |
| V2 | duplex | spi_host_smoke | 17.067m | 15.001ms | 36 | 50 | 72.00 |
| V2 | tx_rx_only | spi_host_smoke | 17.067m | 15.001ms | 36 | 50 | 72.00 |
| V2 | stress_all | spi_host_stress_all | 13.733m | 15.001ms | 40 | 50 | 80.00 |
| V2 | spien | spi_host_spien | 11.667m | 10.001ms | 41 | 50 | 82.00 |
| V2 | stall | spi_host_status_stall | 8.267m | 10.777ms | 38 | 50 | 76.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 8.133m | 10.002ms | 40 | 50 | 80.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 3.850m | 10.349ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 55.858us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 53.210us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 42.545us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 42.545us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 18.291us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 44.552us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 2.000s | 158.398us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 20.143us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 18.291us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 44.552us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 2.000s | 158.398us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 20.143us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 630 | 690 | 91.30 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 305.875us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 132.331us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 305.875us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 44.067m | 176.875ms | 4 | 10 | 40.00 | |
| TOTAL | 760 | 840 | 90.48 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.84 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 30 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
0.spi_host_upper_range_clkdiv.9890607906622290459288350650873210861221362417537290000782214052686951638554
Line 337, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005776185 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3aa4c5d4) == 0x0
UVM_INFO @ 100005776185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_upper_range_clkdiv.35838514513117598842938720552058178815223759078138985606808949594689030885924
Line 313, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100012650964 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcc575f14) == 0x0
UVM_INFO @ 100012650964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 6 failures.
1.spi_host_stress_all.79329100974058055478643300395169145836199615147884214998879691679680432246580
Line 368, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10488949446 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcd7c6d14) == 0x0
UVM_INFO @ 10488949446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_stress_all.86682308200978163346831730326679259855663176980485801629250097668685300693426
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10003049356 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x360ba194) == 0x0
UVM_INFO @ 10003049356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_spien has 6 failures.
1.spi_host_spien.75084426609454171336899550768778170576992285493665455086269090737367978348045
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_spien/latest/run.log
UVM_FATAL @ 10001146559 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x79035694) == 0x0
UVM_INFO @ 10001146559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_spien.45666480448456902630027767704710046020214903746278967534228801660447469074906
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_spien/latest/run.log
UVM_FATAL @ 10000785229 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1f236554) == 0x0
UVM_INFO @ 10000785229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_speed has 5 failures.
3.spi_host_speed.106668346180867067533041319536330727319437827965108861013366051456225955930132
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_speed/latest/run.log
UVM_FATAL @ 10001879770 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x901a8814) == 0x0
UVM_INFO @ 10001879770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.spi_host_speed.75185122895922476988265357978660501336672962916122005171117380075769668546721
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_speed/latest/run.log
UVM_FATAL @ 10003068582 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xba668b14) == 0x0
UVM_INFO @ 10003068582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_smoke has 7 failures.
4.spi_host_smoke.83877864169469720333382062868826611679128530088156621413808892836194549679193
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000967849 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x47ff2f94) == 0x0
UVM_INFO @ 15000967849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_smoke.78872177586897189944406660762670758596262045792851052979462611327013210771805
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000708411 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xacad45d4) == 0x0
UVM_INFO @ 15000708411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
... and 1 more tests.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 18 failures:
Test spi_host_speed has 3 failures.
0.spi_host_speed.34123077343004100678748551754988315537948181573502118873893563658910612856584
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log
UVM_FATAL @ 10081709426 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8ab20a14) == 0x1
UVM_INFO @ 10081709426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_host_speed.77495678433996579390475527688023873858945071237166199959340978064509323006667
Line 437, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_speed/latest/run.log
UVM_FATAL @ 10023090694 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf041f014) == 0x1
UVM_INFO @ 10023090694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_status_stall has 7 failures.
1.spi_host_status_stall.42007481296686905842348713900189909982794933305124610690402718053044831358042
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10034668251 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x40cef4d4) == 0x1
UVM_INFO @ 10034668251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_status_stall.97387661391726295594237071875154990733217194351816257812204253379378991343642
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15007974974 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6fa94894) == 0x1
UVM_INFO @ 15007974974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_host_spien has 2 failures.
4.spi_host_spien.47610756667127961695978394349533625418949690204914822732687594078731358516361
Line 379, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_spien/latest/run.log
UVM_FATAL @ 17926521937 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc4505e94) == 0x1
UVM_INFO @ 17926521937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.spi_host_spien.63830234681550965753964101944441639016140537522835976170612790282333859248097
Line 413, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_spien/latest/run.log
UVM_FATAL @ 10020459559 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf22c4254) == 0x1
UVM_INFO @ 10020459559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_upper_range_clkdiv has 1 failures.
9.spi_host_upper_range_clkdiv.74549996719339219831427214078841610879166326544163567130668185080631648094563
Line 375, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 176874901900 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3ef41914) == 0x1
UVM_INFO @ 176874901900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 3 failures.
22.spi_host_sw_reset.15944253417555948050503792009051285306812629787335300949124600624507109974955
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002722795 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3b2b1454) == 0x1
UVM_INFO @ 10002722795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_sw_reset.6082135393605067000811928371960962786274936770434872037983844383828985111652
Line 374, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10006626816 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x36bc7b54) == 0x1
UVM_INFO @ 10006626816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
... and 1 more tests.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 13 failures:
Test spi_host_speed has 4 failures.
4.spi_host_speed.70414872708906351223731535141846954609157278358445975888488726923228792651084
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_speed/latest/run.log
UVM_FATAL @ 10003918491 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x392d2194) == 0x0
UVM_INFO @ 10003918491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_speed.58304271892794562123106060030228799133661493360749599444236524486930998644149
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_speed/latest/run.log
UVM_FATAL @ 10004480111 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcbb7fb14) == 0x0
UVM_INFO @ 10004480111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_stress_all has 4 failures.
9.spi_host_stress_all.90301269083146794539635284127684838393758388969518025095008490476512710213957
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10000933060 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9f06e014) == 0x0
UVM_INFO @ 10000933060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.spi_host_stress_all.36903206507280592986086222677781020106590687029886800693867865157985520971048
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001207392 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe8d0d8d4) == 0x0
UVM_INFO @ 15001207392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_spien has 1 failures.
18.spi_host_spien.86903059921892473349589001867933729146888033932954836633988805294925911806544
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_spien/latest/run.log
UVM_FATAL @ 10000960458 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xeca03bd4) == 0x0
UVM_INFO @ 10000960458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 4 failures.
26.spi_host_smoke.75674607638013289611897403244809389724330601712478135357395502961163588050233
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000652422 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x996a5994) == 0x0
UVM_INFO @ 15000652422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_smoke.2574746644272226302039268884615750678058710287758851251001166855763215206843
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001363613 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x42c6d954) == 0x0
UVM_INFO @ 15001363613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 8 failures:
5.spi_host_idlecsbactive.17444238141448363921898870043780751859096389886409184075739640178218769030562
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10011025630 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x17b94054) == 0x0
UVM_INFO @ 10011025630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_idlecsbactive.105846104295832639116913972619243352836020799131180440269248277234366142017851
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004344911 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6400b7d4) == 0x0
UVM_INFO @ 10004344911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
1.spi_host_upper_range_clkdiv.50961690795380498186361943589425514255734322439860167287666502495718577046103
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:ffd8234a-dc21-423b-932a-50af198d80c5
6.spi_host_upper_range_clkdiv.62077093872050639246337465261653063378954386808065888350415684865964013794004
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:75f13959-69b8-4468-9cdb-b3f9018e3787
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 3 failures:
Test spi_host_status_stall has 2 failures.
10.spi_host_status_stall.61731841064256030377076903553494747819566307224562850147017786042886557236611
Line 935, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10928873228 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x50d9be54) == 0x1
UVM_INFO @ 10928873228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.spi_host_status_stall.40786510192987753946031916579520165211097132873692958098697513751210011708650
Line 389, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10049130837 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9dc3d514) == 0x1
UVM_INFO @ 10049130837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
29.spi_host_smoke.5846729766320647216062533273291951400313393288412072185787534447511483655000
Line 457, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_smoke/latest/run.log
UVM_FATAL @ 15160229623 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe743b994) == 0x1
UVM_INFO @ 15160229623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 2 failures:
2.spi_host_status_stall.33178259237488481132908196720529670809214493273332906097262513922656351126024
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_ERROR @ 24365450 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 24365450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_status_stall.70632217973559937720005653016982800924225222392773858645220749225770415180082
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log
UVM_ERROR @ 6027025 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 6027025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
23.spi_host_idlecsbactive.92758839506890244924240463499351391615581761741683462946969504056802705637805
Line 407, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.spi_host_idlecsbactive.42362388343046772188438125735942987154260852452248723773755046842433314293396
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:
34.spi_host_status_stall.59137773605338868175323893866839691760889833105202326241458451726427702671274
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_status_stall/latest/run.log
UVM_ERROR @ 4588169 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4588169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---