SPI_HOST Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 18.167m 15.001ms 39 50 78.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 43.747us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 54.940us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 108.287us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 33.960us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 224.308us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 54.940us 20 20 100.00
spi_host_csr_aliasing 3.000s 33.960us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 23.288us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 19.934us 5 5 100.00
V1 TOTAL 104 115 90.43
V2 performance spi_host_performance 4.000s 29.019us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.167m 4.101ms 50 50 100.00
spi_host_error_cmd 3.000s 25.726us 50 50 100.00
spi_host_event 13.217m 19.385ms 50 50 100.00
V2 clock_rate spi_host_speed 11.417m 10.001ms 37 50 74.00
V2 speed spi_host_speed 11.417m 10.001ms 37 50 74.00
V2 chip_select_timing spi_host_speed 11.417m 10.001ms 37 50 74.00
V2 sw_reset spi_host_sw_reset 9.783m 15.213ms 38 50 76.00
V2 passthrough_mode spi_host_passthrough_mode 3.000s 163.137us 50 50 100.00
V2 cpol_cpha spi_host_speed 11.417m 10.001ms 37 50 74.00
V2 full_cycle spi_host_speed 11.417m 10.001ms 37 50 74.00
V2 duplex spi_host_smoke 18.167m 15.001ms 39 50 78.00
V2 tx_rx_only spi_host_smoke 18.167m 15.001ms 39 50 78.00
V2 stress_all spi_host_stress_all 17.517m 15.012ms 40 50 80.00
V2 spien spi_host_spien 11.683m 10.001ms 34 50 68.00
V2 stall spi_host_status_stall 9.167m 23.768ms 28 50 56.00
V2 Idlecsbactive spi_host_idlecsbactive 7.483m 10.002ms 36 50 72.00
V2 data_fifo_status spi_host_overflow_underflow 3.167m 4.101ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 19.474us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 18.367us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 12.000s 124.499us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 12.000s 124.499us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 43.747us 5 5 100.00
spi_host_csr_rw 3.000s 54.940us 20 20 100.00
spi_host_csr_aliasing 3.000s 33.960us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 50.726us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 43.747us 5 5 100.00
spi_host_csr_rw 3.000s 54.940us 20 20 100.00
spi_host_csr_aliasing 3.000s 33.960us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 50.726us 20 20 100.00
V2 TOTAL 603 690 87.39
V2S tl_intg_err spi_host_tl_intg_err 8.000s 125.466us 20 20 100.00
spi_host_sec_cm 2.000s 425.117us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 8.000s 125.466us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 55.783m 100.002ms 1 10 10.00
TOTAL 733 840 87.26

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.77 95.70 100.00 95.07 90.87

Failure Buckets

Past Results