aad711e1bc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 18.167m | 15.001ms | 39 | 50 | 78.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 43.747us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 54.940us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 4.000s | 108.287us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 33.960us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 224.308us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 54.940us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 33.960us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 23.288us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 19.934us | 5 | 5 | 100.00 |
| V1 | TOTAL | 104 | 115 | 90.43 | |||
| V2 | performance | spi_host_performance | 4.000s | 29.019us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.167m | 4.101ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 25.726us | 50 | 50 | 100.00 | ||
| spi_host_event | 13.217m | 19.385ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.417m | 10.001ms | 37 | 50 | 74.00 |
| V2 | speed | spi_host_speed | 11.417m | 10.001ms | 37 | 50 | 74.00 |
| V2 | chip_select_timing | spi_host_speed | 11.417m | 10.001ms | 37 | 50 | 74.00 |
| V2 | sw_reset | spi_host_sw_reset | 9.783m | 15.213ms | 38 | 50 | 76.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 163.137us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.417m | 10.001ms | 37 | 50 | 74.00 |
| V2 | full_cycle | spi_host_speed | 11.417m | 10.001ms | 37 | 50 | 74.00 |
| V2 | duplex | spi_host_smoke | 18.167m | 15.001ms | 39 | 50 | 78.00 |
| V2 | tx_rx_only | spi_host_smoke | 18.167m | 15.001ms | 39 | 50 | 78.00 |
| V2 | stress_all | spi_host_stress_all | 17.517m | 15.012ms | 40 | 50 | 80.00 |
| V2 | spien | spi_host_spien | 11.683m | 10.001ms | 34 | 50 | 68.00 |
| V2 | stall | spi_host_status_stall | 9.167m | 23.768ms | 28 | 50 | 56.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 7.483m | 10.002ms | 36 | 50 | 72.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 3.167m | 4.101ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 19.474us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 18.367us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 12.000s | 124.499us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 12.000s | 124.499us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 43.747us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 54.940us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 33.960us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 50.726us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 43.747us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 54.940us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 33.960us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 50.726us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 603 | 690 | 87.39 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 8.000s | 125.466us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 2.000s | 425.117us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 8.000s | 125.466us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 55.783m | 100.002ms | 1 | 10 | 10.00 | |
| TOTAL | 733 | 840 | 87.26 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.77 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 29 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
1.spi_host_upper_range_clkdiv.68168904103036325160447784868913640676547242486720788225179554189006673149940
Line 337, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005452970 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc2c3f854) == 0x0
UVM_INFO @ 100005452970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_upper_range_clkdiv.104299036186519136267992860554475823017135587217072473319772743194939970234093
Line 307, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003865583 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdac8fcd4) == 0x0
UVM_INFO @ 100003865583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 4 failures.
1.spi_host_spien.17051362059936614891841283766432209557588994134547178810871056674274863074906
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_spien/latest/run.log
UVM_FATAL @ 15004907800 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x265804d4) == 0x0
UVM_INFO @ 15004907800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_spien.10340700403587745097982990027997109465555512920285117453060386963094161965456
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_spien/latest/run.log
UVM_FATAL @ 10001086831 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5a58b514) == 0x0
UVM_INFO @ 10001086831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_stress_all has 6 failures.
2.spi_host_stress_all.87115639317076496622719113408169381255676262447506457672282408043800352582481
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10018594691 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x11020e94) == 0x0
UVM_INFO @ 10018594691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_host_stress_all.100843901811763507179528978051597644700880250853098999333437742006700811997968
Line 414, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22541794103 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdf34a2d4) == 0x0
UVM_INFO @ 22541794103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_smoke has 5 failures.
5.spi_host_smoke.46051016847832259485298647792964115775028577475545266422855130461519430049374
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001192153 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x12122914) == 0x0
UVM_INFO @ 15001192153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_smoke.48870660231476413117113249761195164350803390195085533650194948496237245219461
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_smoke/latest/run.log
UVM_FATAL @ 15004458454 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9418554) == 0x0
UVM_INFO @ 15004458454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_speed has 6 failures.
6.spi_host_speed.33024355584327255487290950189212216398059432760314538651145776221786875185136
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/latest/run.log
UVM_FATAL @ 10000799952 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x317f5494) == 0x0
UVM_INFO @ 10000799952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_speed.100429487640672823704151343176881399032901330743770647988380737750872268031480
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_speed/latest/run.log
UVM_FATAL @ 10000719913 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x721e4254) == 0x0
UVM_INFO @ 10000719913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
... and 2 more tests.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 22 failures:
Test spi_host_spien has 8 failures.
0.spi_host_spien.22492932672236962627927498004174851844768570375503160796953815822650218151372
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 15003926368 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbbf33954) == 0x0
UVM_INFO @ 15003926368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_spien.64248186354184953564063664333959665883741565661620069371626556274843201297588
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_spien/latest/run.log
UVM_FATAL @ 15005092687 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfc82a54) == 0x0
UVM_INFO @ 15005092687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test spi_host_stress_all has 4 failures.
3.spi_host_stress_all.81609029435392997388620796956494315754752063749938100680136947082345484072104
Line 378, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001644355 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1138afd4) == 0x0
UVM_INFO @ 15001644355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_stress_all.33961742373683280962486307009592695348083902356253337673414157424231172516465
Line 429, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15012233083 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa6479ad4) == 0x0
UVM_INFO @ 15012233083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_speed has 5 failures.
5.spi_host_speed.79637984581295787751445750874321070847378990556829100571187355477472922101633
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_speed/latest/run.log
UVM_FATAL @ 10001035380 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6c527a14) == 0x0
UVM_INFO @ 10001035380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_speed.54835031638134206313194142839904790845901278567036244599707290600740179216155
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_speed/latest/run.log
UVM_FATAL @ 10008768389 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfcdcbd94) == 0x0
UVM_INFO @ 10008768389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_upper_range_clkdiv has 2 failures.
8.spi_host_upper_range_clkdiv.78860328968755356114567025539435298431160829333401124512626526816333860728635
Line 323, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003673913 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7840db14) == 0x0
UVM_INFO @ 100003673913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_upper_range_clkdiv.102613105891523240542227509057927945176537641503077535445328044998543695567694
Line 333, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002404914 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x80a3fd94) == 0x0
UVM_INFO @ 100002404914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 3 failures.
39.spi_host_smoke.89135127354774879171486325399575454423192303273852623301551441839814845704354
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_smoke/latest/run.log
UVM_FATAL @ 15003703349 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xca9e18d4) == 0x0
UVM_INFO @ 15003703349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.spi_host_smoke.93872058783405871582507183219776865503386892549290314361083947088770273371656
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000873858 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xae04b5d4) == 0x0
UVM_INFO @ 15000873858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 21 failures:
1.spi_host_status_stall.110466111945067036099466232013820489056855414963075312557448729460072710429481
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10006421163 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xba15bb94) == 0x1
UVM_INFO @ 10006421163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_status_stall.76769295387679961385765921971985898193309656871423383286583779401618163336793
Line 943, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log
UVM_FATAL @ 12631410681 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x21e12714) == 0x1
UVM_INFO @ 12631410681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
6.spi_host_spien.39726345258028932965169412273654176967820635431619907611112903024109330637427
Line 409, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_spien/latest/run.log
UVM_FATAL @ 10048382805 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa6d2e1d4) == 0x1
UVM_INFO @ 10048382805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_spien.42781103234502562287586249728838820741376937447508973079387865438055582116255
Line 415, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_spien/latest/run.log
UVM_FATAL @ 10017270044 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1e3a3414) == 0x1
UVM_INFO @ 10017270044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
16.spi_host_sw_reset.11412325753596658225554468101126031704669185620504538708334996348525447246349
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10012017880 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x277b1d94) == 0x1
UVM_INFO @ 10012017880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_host_sw_reset.71251118738760489407474269851804865458202133728385261854880808505317202795420
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10039525590 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9e169c54) == 0x1
UVM_INFO @ 10039525590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
23.spi_host_smoke.110226810284199550250853744607395212635728528060186217503225212595853884420188
Line 473, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_smoke/latest/run.log
UVM_FATAL @ 18438344979 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5e7240d4) == 0x1
UVM_INFO @ 18438344979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.spi_host_smoke.15417109048329173581677228783100854904552581732218525182119730517531472486483
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_smoke/latest/run.log
UVM_FATAL @ 15193942028 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6959f094) == 0x1
UVM_INFO @ 15193942028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 14 failures:
Test spi_host_idlecsbactive has 12 failures.
2.spi_host_idlecsbactive.69126331745399226068877945938892442909257198405308724627044820598728324352850
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10012898543 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb8460794) == 0x0
UVM_INFO @ 10012898543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_idlecsbactive.67537922907892014602651102984106600478220093122371437405842094514961684191244
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10018862484 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xdccfcad4) == 0x0
UVM_INFO @ 10018862484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Test spi_host_upper_range_clkdiv has 1 failures.
5.spi_host_upper_range_clkdiv.115262043185879437852997739255667019333195721844338330057336660452202327775305
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 153542393215 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5c685e14) == 0x0
UVM_INFO @ 153542393215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
39.spi_host_status_stall.41256287772338051275772134874295896210380878602704704183516797924377283294142
Line 1014, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_status_stall/latest/run.log
UVM_FATAL @ 47250486269 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x184b3414) == 0x0
UVM_INFO @ 47250486269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 9 failures:
Test spi_host_speed has 2 failures.
22.spi_host_speed.103676325760565668026513407481330075126586304852066096816569800809437321487470
Line 401, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_speed/latest/run.log
UVM_FATAL @ 10058764524 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x33975b54) == 0x1
UVM_INFO @ 10058764524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_speed.37578814557089520645182460569475576033593454871232696295589178125925599557672
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_speed/latest/run.log
UVM_FATAL @ 10065517065 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2f50f714) == 0x1
UVM_INFO @ 10065517065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 3 failures.
22.spi_host_status_stall.50038648150437560920913184011054804957564485043824854986136820604508807640155
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15004200012 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc803ced4) == 0x1
UVM_INFO @ 15004200012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.spi_host_status_stall.17946276071632051317105110636597288428668385588113176587572997150079474230183
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10019230482 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xdfec3bd4) == 0x1
UVM_INFO @ 10019230482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_sw_reset has 2 failures.
34.spi_host_sw_reset.9360945991554901480929612968277299550996554048356574600311555137935999199192
Line 346, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10011661123 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x88efb54) == 0x1
UVM_INFO @ 10011661123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.spi_host_sw_reset.94584274702213857962936045231305052765469941410632974346069983402123143193513
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15004315452 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x764a8054) == 0x1
UVM_INFO @ 15004315452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
34.spi_host_spien.101082339103140516293894186505942280069400352620468041740817340947194761598579
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_spien/latest/run.log
UVM_FATAL @ 10051590723 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8111fc54) == 0x1
UVM_INFO @ 10051590723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
49.spi_host_smoke.18000041206549908734128676714586227574156408358931436821465211941745083832996
Line 367, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_smoke/latest/run.log
UVM_FATAL @ 10035245178 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcada4d94) == 0x1
UVM_INFO @ 10035245178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
2.spi_host_upper_range_clkdiv.36630855507953749057531140897124751265888522581862121854014210600861854513794
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:3145b9aa-a454-4ca6-bd7e-54bb0b06f2da
3.spi_host_upper_range_clkdiv.63744315488169250484032946886799255018635185181705207746766531226761471024510
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:3c831916-d905-4d46-a016-0186891d8e81
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 3 failures:
10.spi_host_status_stall.37301427886489006896601152575104605220049957421995590319732435058003104790753
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
UVM_ERROR @ 2992269 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2992269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_host_status_stall.45686860915195139130235365464196073743672962289806536737758687012818880297725
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
UVM_ERROR @ 22338044 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 22338044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 3 failures:
20.spi_host_status_stall.47486440814596003046507931145980466839725936101278846764913966500552418295632
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log
UVM_ERROR @ 7016128 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 7016128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_host_status_stall.111179465865386868718008254189857899372829625885483958041500976810099374985139
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_status_stall/latest/run.log
UVM_ERROR @ 1666844 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 1666844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 2 failures:
31.spi_host_idlecsbactive.24255735156973488566012868977805376360801113867097641168342509515124862414455
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15047692335 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x497faa14) == 0x0
UVM_INFO @ 15047692335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.spi_host_idlecsbactive.45048057487140537778463557741541176639401465626561961905790433113064265033562
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002607584 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xba3ef4d4) == 0x0
UVM_INFO @ 10002607584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---