SPI_HOST Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.867m 15.002ms 36 50 72.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 36.728us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 18.714us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 382.088us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 25.868us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 42.808us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 18.714us 20 20 100.00
spi_host_csr_aliasing 3.000s 25.868us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 52.034us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 121.990us 5 5 100.00
V1 TOTAL 101 115 87.83
V2 performance spi_host_performance 4.000s 71.216us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.450m 17.204ms 50 50 100.00
spi_host_error_cmd 3.000s 15.656us 50 50 100.00
spi_host_event 14.617m 21.989ms 50 50 100.00
V2 clock_rate spi_host_speed 11.000m 10.001ms 40 50 80.00
V2 speed spi_host_speed 11.000m 10.001ms 40 50 80.00
V2 chip_select_timing spi_host_speed 11.000m 10.001ms 40 50 80.00
V2 sw_reset spi_host_sw_reset 10.167m 15.002ms 37 50 74.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 161.618us 50 50 100.00
V2 cpol_cpha spi_host_speed 11.000m 10.001ms 40 50 80.00
V2 full_cycle spi_host_speed 11.000m 10.001ms 40 50 80.00
V2 duplex spi_host_smoke 10.867m 15.002ms 36 50 72.00
V2 tx_rx_only spi_host_smoke 10.867m 15.002ms 36 50 72.00
V2 stress_all spi_host_stress_all 24.450m 22.501ms 39 50 78.00
V2 spien spi_host_spien 7.783m 15.004ms 39 50 78.00
V2 stall spi_host_status_stall 11.433m 15.299ms 38 50 76.00
V2 Idlecsbactive spi_host_idlecsbactive 7.500m 10.003ms 41 50 82.00
V2 data_fifo_status spi_host_overflow_underflow 3.450m 17.204ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 36.275us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 124.177us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 418.565us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 418.565us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 36.728us 5 5 100.00
spi_host_csr_rw 3.000s 18.714us 20 20 100.00
spi_host_csr_aliasing 3.000s 25.868us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 22.191us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 36.728us 5 5 100.00
spi_host_csr_rw 3.000s 18.714us 20 20 100.00
spi_host_csr_aliasing 3.000s 25.868us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 22.191us 20 20 100.00
V2 TOTAL 624 690 90.43
V2S tl_intg_err spi_host_tl_intg_err 4.000s 352.956us 20 20 100.00
spi_host_sec_cm 3.000s 303.264us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 352.956us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 44.533m 100.002ms 0 10 0.00
TOTAL 750 840 89.29

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results