8b2da8db5e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 10.867m | 15.002ms | 36 | 50 | 72.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 36.728us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 18.714us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 382.088us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 25.868us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 42.808us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 18.714us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 25.868us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 52.034us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 121.990us | 5 | 5 | 100.00 |
| V1 | TOTAL | 101 | 115 | 87.83 | |||
| V2 | performance | spi_host_performance | 4.000s | 71.216us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.450m | 17.204ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 15.656us | 50 | 50 | 100.00 | ||
| spi_host_event | 14.617m | 21.989ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.000m | 10.001ms | 40 | 50 | 80.00 |
| V2 | speed | spi_host_speed | 11.000m | 10.001ms | 40 | 50 | 80.00 |
| V2 | chip_select_timing | spi_host_speed | 11.000m | 10.001ms | 40 | 50 | 80.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.167m | 15.002ms | 37 | 50 | 74.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 161.618us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.000m | 10.001ms | 40 | 50 | 80.00 |
| V2 | full_cycle | spi_host_speed | 11.000m | 10.001ms | 40 | 50 | 80.00 |
| V2 | duplex | spi_host_smoke | 10.867m | 15.002ms | 36 | 50 | 72.00 |
| V2 | tx_rx_only | spi_host_smoke | 10.867m | 15.002ms | 36 | 50 | 72.00 |
| V2 | stress_all | spi_host_stress_all | 24.450m | 22.501ms | 39 | 50 | 78.00 |
| V2 | spien | spi_host_spien | 7.783m | 15.004ms | 39 | 50 | 78.00 |
| V2 | stall | spi_host_status_stall | 11.433m | 15.299ms | 38 | 50 | 76.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 7.500m | 10.003ms | 41 | 50 | 82.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 3.450m | 17.204ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 36.275us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 124.177us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 418.565us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 418.565us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 36.728us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 18.714us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 25.868us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 22.191us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 36.728us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 18.714us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 25.868us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 22.191us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 624 | 690 | 90.43 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 352.956us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 303.264us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 352.956us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 44.533m | 100.002ms | 0 | 10 | 0.00 | |
| TOTAL | 750 | 840 | 89.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.84 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 33 failures:
Test spi_host_speed has 5 failures.
0.spi_host_speed.86110496323411859696497453472232666117649696844782612709602562271425572255314
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log
UVM_FATAL @ 10004262722 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x874f9894) == 0x0
UVM_INFO @ 10004262722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_speed.75400167092291681283591231969510517999719703787313545013634543206370135065415
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_speed/latest/run.log
UVM_FATAL @ 10004728438 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9470f954) == 0x0
UVM_INFO @ 10004728438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_upper_range_clkdiv has 2 failures.
1.spi_host_upper_range_clkdiv.99308568517984762054568060237062605926597853544247652867706430314620192391989
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002431710 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x28199614) == 0x0
UVM_INFO @ 100002431710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_upper_range_clkdiv.32121533075831611044283068573029733746266816079702250485572471124656099320125
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004274145 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x822ecd54) == 0x0
UVM_INFO @ 100004274145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 6 failures.
4.spi_host_spien.56681381844668387226331582407100803578622216033202033445609535509398579107472
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_spien/latest/run.log
UVM_FATAL @ 10001647858 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x868bd854) == 0x0
UVM_INFO @ 10001647858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_spien.76797154111444802474709860738075460606174379788750368491549411025410487914934
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_spien/latest/run.log
UVM_FATAL @ 15004497248 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xaccbf794) == 0x0
UVM_INFO @ 15004497248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_smoke has 7 failures.
5.spi_host_smoke.100051080145179959595909596846289614745229287164521177090758292669732796408202
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
UVM_FATAL @ 15003480059 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc1765014) == 0x0
UVM_INFO @ 15003480059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_smoke.39598624216933750458545300626782324306827077408391759339970285267915168760568
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_smoke/latest/run.log
UVM_FATAL @ 15005399388 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6c1bce54) == 0x0
UVM_INFO @ 15005399388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_host_sw_reset has 9 failures.
7.spi_host_sw_reset.40528623863050981837117971108952963701296915866135862709328028482207531297779
Line 330, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10011719849 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x30c3ecd4) == 0x0
UVM_INFO @ 10011719849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_sw_reset.93338605992829842070024412589342101778168199870706828493107827026955901097645
Line 389, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10060080268 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xec539d94) == 0x0
UVM_INFO @ 10060080268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
... and 2 more tests.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*) == * has 19 failures:
Test spi_host_smoke has 6 failures.
0.spi_host_smoke.11215220236356250649192248800464277511711669167743607376846231098233733884685
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001273310 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb0a16a14) == 0x0
UVM_INFO @ 15001273310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_smoke.99346022487727705920132878355913662296919883448863888619665105952820439514851
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
UVM_FATAL @ 15004441547 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcbfc52d4) == 0x0
UVM_INFO @ 15004441547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_stress_all has 7 failures.
0.spi_host_stress_all.106731359907317962001289110709228864430278123563419539057513711988563767525471
Line 346, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22502189838 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3f28e454) == 0x0
UVM_INFO @ 22502189838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_stress_all.50869573964636583637436639176141094590991100446661098782736560555812908927613
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15000721999 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5e15da14) == 0x0
UVM_INFO @ 15000721999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_host_spien has 2 failures.
0.spi_host_spien.106584777029249043904537232060432718159317401965512263289536239563484135726686
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 10002017979 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x59fac494) == 0x0
UVM_INFO @ 10002017979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_spien.114711521153763970043857836169764236194003991867848820649948370302501880405038
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_spien/latest/run.log
UVM_FATAL @ 10001996096 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3cb8e554) == 0x0
UVM_INFO @ 10001996096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_upper_range_clkdiv has 1 failures.
2.spi_host_upper_range_clkdiv.41152558365650094151787257878725412980295622798155149368354782708132120323802
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100015378405 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x92219954) == 0x0
UVM_INFO @ 100015378405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 3 failures.
6.spi_host_speed.55554887287599270298940342848482946401588695668602974829306787485221878367224
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/latest/run.log
UVM_FATAL @ 10003432142 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x88425354) == 0x0
UVM_INFO @ 10003432142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_host_speed.70781324996713425181098960787794567417832980240698603137916155952635690067820
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_speed/latest/run.log
UVM_FATAL @ 10002969463 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x78415f14) == 0x0
UVM_INFO @ 10002969463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 17 failures:
Test spi_host_sw_reset has 3 failures.
1.spi_host_sw_reset.29484710722015446460157651211742994171489120117062810079737774032694015052117
Line 366, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15005851515 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xaa23c414) == 0x1
UVM_INFO @ 15005851515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_sw_reset.22136077832912599639684836279802884654233223924186653198049925164245253379494
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10018304990 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5c58fe14) == 0x1
UVM_INFO @ 10018304990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_status_stall has 8 failures.
4.spi_host_status_stall.7961527048652404276980875456049320487556292929222082177643156814928993087105
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10005389610 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc2c4e994) == 0x1
UVM_INFO @ 10005389610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_status_stall.23193048540879476116799607129489357604282772741386492558819365250577412159191
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15299001310 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x38ffe094) == 0x1
UVM_INFO @ 15299001310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test spi_host_smoke has 1 failures.
12.spi_host_smoke.22453862176161907314686878284663608650777289367321789700770177529033773249385
Line 385, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_smoke/latest/run.log
UVM_FATAL @ 15618241958 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9cc9d654) == 0x1
UVM_INFO @ 15618241958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 3 failures.
26.spi_host_spien.77367809448180241528751433818077842296052735218980399207216121452838317136540
Line 415, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_spien/latest/run.log
UVM_FATAL @ 10079463540 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe5568354) == 0x1
UVM_INFO @ 10079463540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_host_spien.41159275633188000611515545187503382757901821507221325691112176027349688796675
Line 407, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_spien/latest/run.log
UVM_FATAL @ 10012974470 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x11447894) == 0x1
UVM_INFO @ 10012974470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_speed has 2 failures.
30.spi_host_speed.96921652294736864624046278847575796399114775241063438816010664080476247463831
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_speed/latest/run.log
UVM_FATAL @ 10024126695 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa775f294) == 0x1
UVM_INFO @ 10024126695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_speed.85823053180188571842843039825934332503122876338380615568394456687330905956641
Line 417, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_speed/latest/run.log
UVM_FATAL @ 10011016139 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3c286d14) == 0x1
UVM_INFO @ 10011016139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 7 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
0.spi_host_upper_range_clkdiv.84090398622098732344465045384739318969526433976981557082217538236108177493855
Line 329, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003655093 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x38e313d4) == 0x0
UVM_INFO @ 100003655093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_upper_range_clkdiv.50863668331713435272356441713931139560637557330983722751888233055892766047227
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 185477034261 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x157a8ad4) == 0x0
UVM_INFO @ 185477034261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_idlecsbactive has 5 failures.
0.spi_host_idlecsbactive.11246776521416055888068068436033968553556082478848604128717022154213300015467
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10011264455 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x72de07d4) == 0x0
UVM_INFO @ 10011264455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_idlecsbactive.87599809056000030690503538989595264911468818368805449944966744712935095514068
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10008388909 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x305b4994) == 0x0
UVM_INFO @ 10008388909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
3.spi_host_upper_range_clkdiv.76588768376109474740768040713851473727904750748789391525158790452134852959438
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:44e8e4ca-725c-43d0-af82-12eab93c2923
6.spi_host_upper_range_clkdiv.67439028823038741490240192397645671167866734424736907721082739640010038886470
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:6c9466ca-e642-4a84-a6f3-f9f8eb992e6e
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
4.spi_host_upper_range_clkdiv.56820681665916428166943464990601431036391256174907065391858948656024927342252
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_upper_range_clkdiv.77715200381448253540539915865139846581380974548951011852608559318449242967409
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_idlecsbactive has 1 failures.
45.spi_host_idlecsbactive.38658530147880354038522448621644939686130535398138424186365360051175075798845
Line 395, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*) == * has 3 failures:
33.spi_host_idlecsbactive.23582010282123544524699188850676936024758919589861721452810984026440077162303
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10016182158 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf3fa6214) == 0x0
UVM_INFO @ 10016182158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_host_idlecsbactive.67100611895248970793643180499752669092139001641881710885042101833033204536965
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002563425 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x695ed214) == 0x0
UVM_INFO @ 10002563425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:
5.spi_host_status_stall.55281369427104489681629586607741430577660551310394537259619386959158836109393
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log
UVM_ERROR @ 8567390 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 8567390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.spi_host_status_stall.70049551091940309072012858651946771664559265176048871768334991892742164484753
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_status_stall/latest/run.log
UVM_ERROR @ 6042801 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6042801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*) == * has 2 failures:
Test spi_host_sw_reset has 1 failures.
32.spi_host_sw_reset.571732394969673007453166069358719621541382796651395733184155120924836148088
Line 366, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10012263244 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xdc96e254) == 0x1
UVM_INFO @ 10012263244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
48.spi_host_stress_all.63105237137021150451763070812957300918574081680594951962945165268676508868406
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10027110490 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa48ec5d4) == 0x1
UVM_INFO @ 10027110490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 1 failures:
29.spi_host_status_stall.46723062162557682218951827904985622847461529021893363342279913527209827866385
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
UVM_ERROR @ 13323016 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 13323016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---