974aaab627| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 16.183m | 15.001ms | 29 | 50 | 58.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 18.840us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 19.867us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 60.659us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 4.000s | 29.829us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 33.135us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 19.867us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 4.000s | 29.829us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 24.662us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 23.974us | 5 | 5 | 100.00 |
| V1 | TOTAL | 94 | 115 | 81.74 | |||
| V2 | performance | spi_host_performance | 4.000s | 138.852us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.717m | 35.234ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 45.575us | 50 | 50 | 100.00 | ||
| spi_host_event | 5.750m | 16.968ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 9.767m | 10.001ms | 43 | 50 | 86.00 |
| V2 | speed | spi_host_speed | 9.767m | 10.001ms | 43 | 50 | 86.00 |
| V2 | chip_select_timing | spi_host_speed | 9.767m | 10.001ms | 43 | 50 | 86.00 |
| V2 | sw_reset | spi_host_sw_reset | 7.533m | 10.013ms | 39 | 50 | 78.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 396.622us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 9.767m | 10.001ms | 43 | 50 | 86.00 |
| V2 | full_cycle | spi_host_speed | 9.767m | 10.001ms | 43 | 50 | 86.00 |
| V2 | duplex | spi_host_smoke | 16.183m | 15.001ms | 29 | 50 | 58.00 |
| V2 | tx_rx_only | spi_host_smoke | 16.183m | 15.001ms | 29 | 50 | 58.00 |
| V2 | stress_all | spi_host_stress_all | 16.667m | 15.002ms | 42 | 50 | 84.00 |
| V2 | spien | spi_host_spien | 12.033m | 16.177ms | 35 | 50 | 70.00 |
| V2 | stall | spi_host_status_stall | 7.833m | 10.002ms | 34 | 50 | 68.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 12.333m | 200.000ms | 35 | 50 | 70.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.717m | 35.234ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 18.222us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 4.000s | 49.862us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 356.443us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 356.443us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 18.840us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 19.867us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 4.000s | 29.829us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 154.609us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 18.840us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 19.867us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 4.000s | 29.829us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 154.609us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 618 | 690 | 89.57 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 204.323us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 232.376us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 204.323us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 51.117m | 100.004ms | 1 | 10 | 10.00 | |
| TOTAL | 738 | 840 | 87.86 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.84 | 95.70 | 100.00 | 95.07 | 90.87 |
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 24 failures:
Test spi_host_spien has 7 failures.
0.spi_host_spien.82261046109984015834870826933782801040797730191630865383265100370733960119859
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 15001986297 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc71a6314, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001986297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_spien.39528034963231218850007193497336245481022681734364121651608105413174650662508
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_spien/latest/run.log
UVM_FATAL @ 10000857320 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x42e4aad4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000857320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_host_smoke has 9 failures.
1.spi_host_smoke.92797643004821951773494753983616933518893767829839802767045680178892287011678
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001438289 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdf089014, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001438289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_smoke.38495028784011501954656270298641613681944941977345847337610102082291270290079
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_smoke/latest/run.log
UVM_FATAL @ 15005000045 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x94cab814, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15005000045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test spi_host_speed has 3 failures.
3.spi_host_speed.16620283999918397472302217834444601924857172602652156328771578036390985637819
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_speed/latest/run.log
UVM_FATAL @ 10001420024 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc567fb94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001420024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.spi_host_speed.58263437417915464118966366809213770721176308338846909169219775519662203032589
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_speed/latest/run.log
UVM_FATAL @ 10001751158 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x588c5dd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001751158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_upper_range_clkdiv has 2 failures.
6.spi_host_upper_range_clkdiv.18579804125809444394075396016160558927938758212085897669976336694190952324780
Line 337, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003793268 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc0112514, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003793268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_upper_range_clkdiv.60241772939895533141822422391050996545981576817664761704004810080368088541006
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002261789 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe70ab6d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100002261789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 3 failures.
8.spi_host_stress_all.63992404235488887240619085046676648383272639572215192671113615053794892368342
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10002786707 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd343d794, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002786707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_stress_all.61134462425779678774177965614499147030969956156652107912432415462179607102424
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001665884 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x78dcadd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001665884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 20 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
2.spi_host_upper_range_clkdiv.108311334121640331772173675938937449257645071743189260251899120673064460384649
Line 307, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100000863914 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x896aa094, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100000863914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_upper_range_clkdiv.72863012593584283922722729667289288066548514798018079208444847775896640776904
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003584663 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8bb99914, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003584663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 3 failures.
4.spi_host_speed.67960827871462845408268500291490266687103277475708487419233196481272571975624
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_speed/latest/run.log
UVM_FATAL @ 10000925976 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5d174fd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000925976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_speed.87878183085942042753952181505486267630644653470520402568154342114775273007788
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_speed/latest/run.log
UVM_FATAL @ 10001315777 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfeca3394, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001315777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_smoke has 10 failures.
8.spi_host_smoke.108399464436445178334663619721421504318416599016649699058467348347208309038486
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_smoke/latest/run.log
UVM_FATAL @ 15009986173 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1758e154, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15009986173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_smoke.61219438926546793835111837170289895672435516921263889744415190784277770549488
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001016975 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x56757394, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001016975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test spi_host_stress_all has 2 failures.
18.spi_host_stress_all.104560889530604219886339365628238590761207283425650355358733691237271984960868
Line 374, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15008255482 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1a7511d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15008255482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.spi_host_stress_all.64825656879432835097625358110016770059962812953258280198075215494073613845922
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15007379712 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1f055294, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15007379712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 3 failures.
27.spi_host_spien.59053403154868618974790318163169685324462311883059005478305647429704949589316
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_spien/latest/run.log
UVM_FATAL @ 10001258407 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe2e37154, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001258407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_spien.98738142466774054446347351807775212270483715193498392297123819149123210415064
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_spien/latest/run.log
UVM_FATAL @ 10004804324 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc2d4db14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004804324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
0.spi_host_upper_range_clkdiv.77607697745158189587089285823446983028403938682939673008722045035482429714600
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:ab150431-cf4c-4a8d-9272-b4933ab45afe
1.spi_host_upper_range_clkdiv.107868745031618375944034503082311762840326895532875890342335350282371347438753
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:9fe14114-b14e-4e75-87b2-74bc16aac713
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 5 failures:
5.spi_host_idlecsbactive.60175576941642042175354659563674807187638612051585584509233988455096447556812
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10015094785 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf7637354, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10015094785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_idlecsbactive.67111670091204088928245781782804665593773805518434203626248854406650343016635
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10011251394 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x46fd3c54, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10011251394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 4 failures:
3.spi_host_status_stall.15051553411524148311559717032409923237051827054187938752914357080613158017794
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15013814355 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xca422214, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 15013814355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_host_status_stall.36570790937280838578111817528824788439198939926558691267153138457327688955611
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10007067964 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x36494954, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10007067964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 4 failures:
7.spi_host_idlecsbactive.27166887655623324221496726327687980241847958728189835627014909282477026550128
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10005679299 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x23887454, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10005679299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.spi_host_idlecsbactive.104499960583152997017551762902746747297292696049586005018002526968177702513730
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004755464 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xabc9c94, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10004755464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 3 failures:
31.spi_host_idlecsbactive.33931270553760713408408276156628403270737394562925928483319308716156026624673
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15004089554 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2d7f7314, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15004089554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_host_idlecsbactive.7125127400390667776387009009974764717543156666546703306037414961473218169196
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15003141531 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5cf5fb14, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15003141531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 3 failures:
34.spi_host_status_stall.71025776713404725144703579076426146492678956422006714125608468830042962259846
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_status_stall/latest/run.log
UVM_ERROR @ 5114176 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 5114176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.spi_host_status_stall.24437878492226071190604428154959690786880348920637980444862356297472835707396
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_status_stall/latest/run.log
UVM_ERROR @ 4804441 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 4804441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
2.spi_host_sw_reset.26663198777984775126101276799571882819669403248910809337309182556790098030062
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001770825 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9279c094, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10001770825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_host_sw_reset.9733985562074654630837235048488286839933017612165710542795675012668250063062
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10018084047 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9631c14, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10018084047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 2 failures:
2.spi_host_stress_all.42878624118328143279180296183939821323917195948415876225555329726303686089643
Line 427, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15012952857 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x114b61d4, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 15012952857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_stress_all.62483639097581929928120829298789378737634484690422524050593263168408523733605
Line 414, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10012812472 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa4099594, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10012812472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
6.spi_host_status_stall.31444277294045711630415049913841769334589714766946927417058045077221612344237
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10001660538 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x494d15d4, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10001660538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_host_status_stall.7339908912198374523117649245862650407652920115584061116863194493073517345471
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10004191591 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf2fda854, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10004191591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
Test spi_host_status_stall has 1 failures.
11.spi_host_status_stall.42108387275749122508925984026872033450999409009842904033244790028678879481201
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10004369794 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x31d094, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10004369794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 1 failures.
30.spi_host_sw_reset.17796272389477543719106668004498633247868617024876861756078799968118174659785
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002980599 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4e594dd4, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10002980599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
17.spi_host_idlecsbactive.101473606332474705688033973684531622987235084798999816594773632443946792957974
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002344305 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5d313554, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10002344305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.spi_host_idlecsbactive.85963955198991657083365249540310920767688735129183518518513731625436593327279
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002556312 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xaa96dcd4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10002556312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
Test spi_host_status_stall has 1 failures.
19.spi_host_status_stall.8756529913229865295682829377493046798207019947424987282823822509802636370905
Line 367, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15022749819 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2b1825d4, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 15022749819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 1 failures.
39.spi_host_sw_reset.88724950312969800517033550278301226737027761029461772810135707014274584288385
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10015730361 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x74125414, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10015730361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 2 failures:
Test spi_host_sw_reset has 1 failures.
41.spi_host_sw_reset.39649041189623509839002143073002363158926819480858443539877804206176625894564
Line 427, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10012845961 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x13638794, Comparison=CompareOpEq, exp_data=0x1, call_count=30)
UVM_INFO @ 10012845961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
46.spi_host_smoke.15291309794160372020904732362826243946572523013185655356722536212870782778840
Line 417, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_smoke/latest/run.log
UVM_FATAL @ 15845671489 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd57a0694, Comparison=CompareOpEq, exp_data=0x1, call_count=30)
UVM_INFO @ 15845671489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
2.spi_host_idlecsbactive.66978662526982159370473609298772157362570847344170345510848412176743578153953
Line 407, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
5.spi_host_spien.100971630438994896345616536462799572962690395078005885379801962359497159397776
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_spien/latest/run.log
UVM_FATAL @ 10042952658 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x28950ed4, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10042952658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
11.spi_host_sw_reset.101731097920872306318605339259206655344609185712489460057744208029557690305914
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10024378705 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa5d87794, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
UVM_INFO @ 10024378705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
17.spi_host_sw_reset.43983850025560767112747946134706431798788762809422285165967348651460548944322
Line 316, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003349328 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x450035d4, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10003349328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=38) has 1 failures:
19.spi_host_smoke.22296257149987507753610911166650283468442211280485279267112482980368691383993
Line 447, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_smoke/latest/run.log
UVM_FATAL @ 17959127117 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfaea9754, Comparison=CompareOpEq, exp_data=0x1, call_count=38)
UVM_INFO @ 17959127117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=51) has 1 failures:
19.spi_host_sw_reset.69283956403346662235340045391132781294859599650880517717078868358273731322423
Line 528, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10095163574 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x87fa4454, Comparison=CompareOpEq, exp_data=0x0, call_count=51)
UVM_INFO @ 10095163574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=32) has 1 failures:
21.spi_host_stress_all.44886584689151175337160248636792807957203017835548090233103792553748435493978
Line 493, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10097797218 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x899c4ed4, Comparison=CompareOpEq, exp_data=0x0, call_count=32)
UVM_INFO @ 10097797218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
21.spi_host_spien.14986854703846930653532278789359188748146965940411140005251696311639295225335
Line 389, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_spien/latest/run.log
UVM_FATAL @ 10020428895 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfdc7ef54, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 10020428895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=56) has 1 failures:
23.spi_host_status_stall.17331962779356036677556923446148382384764774526468018742456114530953625694534
Line 679, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log
UVM_FATAL @ 16422012479 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9e13b7d4, Comparison=CompareOpEq, exp_data=0x1, call_count=56)
UVM_INFO @ 16422012479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=33) has 1 failures:
27.spi_host_sw_reset.93649566105577555062998629130461218908780056115226662645551618455660035938062
Line 436, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10036426656 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1ab04d14, Comparison=CompareOpEq, exp_data=0x0, call_count=33)
UVM_INFO @ 10036426656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
27.spi_host_status_stall.113417666484691927670018353435106259014968158912848659279185976043458926135829
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10005088461 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd29fd8d4, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10005088461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=87) has 1 failures:
32.spi_host_status_stall.71818817163792469635513965358683882167271117859101161225529408537591978538086
Line 925, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10943178465 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x66840914, Comparison=CompareOpEq, exp_data=0x1, call_count=87)
UVM_INFO @ 10943178465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
33.spi_host_status_stall.30021177987200727510602346399819759677844571519625707771093630177540427360262
Line 409, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10024593100 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x30f26094, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10024593100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
34.spi_host_spien.93875034123469023765062047975780720615350751844773471902473301745071496009380
Line 411, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_spien/latest/run.log
UVM_FATAL @ 10022752477 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x12beb014, Comparison=CompareOpEq, exp_data=0x1, call_count=27)
UVM_INFO @ 10022752477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=55) has 1 failures:
37.spi_host_spien.6878859304840617160729275053754161637003557875685322441434797678284558942143
Line 515, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_spien/latest/run.log
UVM_FATAL @ 10381123167 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x429e7014, Comparison=CompareOpEq, exp_data=0x1, call_count=55)
UVM_INFO @ 10381123167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=36) has 1 failures:
40.spi_host_speed.30267247625274438845860086340236788387991478461636122435239941787615228306388
Line 437, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_speed/latest/run.log
UVM_FATAL @ 10143176265 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4c1e0614, Comparison=CompareOpEq, exp_data=0x1, call_count=36)
UVM_INFO @ 10143176265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
40.spi_host_sw_reset.83209199435835345719665783216123310065196700454579114534856546121322570854579
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10008643910 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb229614, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10008643910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=41) has 1 failures:
42.spi_host_spien.13763159572235166539184427540378973797165245407308686152346374809889147623498
Line 495, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_spien/latest/run.log
UVM_FATAL @ 16177254100 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa0c38914, Comparison=CompareOpEq, exp_data=0x1, call_count=41)
UVM_INFO @ 16177254100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
44.spi_host_sw_reset.80266434784907081466393840794229622412660750281232203993928918134219681205456
Line 340, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003927211 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1d164e14, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10003927211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=94) has 1 failures:
44.spi_host_status_stall.95855418048382381814216391848196428849360443684853569632662261775397104822933
Line 971, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10622746602 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7211cc14, Comparison=CompareOpEq, exp_data=0x1, call_count=94)
UVM_INFO @ 10622746602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---