SPI_HOST Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 16.183m 15.001ms 29 50 58.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 18.840us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 19.867us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 60.659us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 29.829us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 33.135us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 19.867us 20 20 100.00
spi_host_csr_aliasing 4.000s 29.829us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 24.662us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 23.974us 5 5 100.00
V1 TOTAL 94 115 81.74
V2 performance spi_host_performance 4.000s 138.852us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.717m 35.234ms 50 50 100.00
spi_host_error_cmd 3.000s 45.575us 50 50 100.00
spi_host_event 5.750m 16.968ms 50 50 100.00
V2 clock_rate spi_host_speed 9.767m 10.001ms 43 50 86.00
V2 speed spi_host_speed 9.767m 10.001ms 43 50 86.00
V2 chip_select_timing spi_host_speed 9.767m 10.001ms 43 50 86.00
V2 sw_reset spi_host_sw_reset 7.533m 10.013ms 39 50 78.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 396.622us 50 50 100.00
V2 cpol_cpha spi_host_speed 9.767m 10.001ms 43 50 86.00
V2 full_cycle spi_host_speed 9.767m 10.001ms 43 50 86.00
V2 duplex spi_host_smoke 16.183m 15.001ms 29 50 58.00
V2 tx_rx_only spi_host_smoke 16.183m 15.001ms 29 50 58.00
V2 stress_all spi_host_stress_all 16.667m 15.002ms 42 50 84.00
V2 spien spi_host_spien 12.033m 16.177ms 35 50 70.00
V2 stall spi_host_status_stall 7.833m 10.002ms 34 50 68.00
V2 Idlecsbactive spi_host_idlecsbactive 12.333m 200.000ms 35 50 70.00
V2 data_fifo_status spi_host_overflow_underflow 2.717m 35.234ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 18.222us 50 50 100.00
V2 intr_test spi_host_intr_test 4.000s 49.862us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 356.443us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 356.443us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 18.840us 5 5 100.00
spi_host_csr_rw 3.000s 19.867us 20 20 100.00
spi_host_csr_aliasing 4.000s 29.829us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 154.609us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 18.840us 5 5 100.00
spi_host_csr_rw 3.000s 19.867us 20 20 100.00
spi_host_csr_aliasing 4.000s 29.829us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 154.609us 20 20 100.00
V2 TOTAL 618 690 89.57
V2S tl_intg_err spi_host_tl_intg_err 4.000s 204.323us 20 20 100.00
spi_host_sec_cm 3.000s 232.376us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 204.323us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 51.117m 100.004ms 1 10 10.00
TOTAL 738 840 87.86

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results