SPI_HOST Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.217m 49.758ms 39 50 78.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 32.666us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 46.818us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 4.466ms 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 31.476us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 24.191us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 46.818us 20 20 100.00
spi_host_csr_aliasing 3.000s 31.476us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 46.074us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 22.923us 5 5 100.00
V1 TOTAL 104 115 90.43
V2 performance spi_host_performance 3.000s 101.690us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.283m 11.470ms 50 50 100.00
spi_host_error_cmd 3.000s 46.411us 50 50 100.00
spi_host_event 28.300m 75.062ms 50 50 100.00
V2 clock_rate spi_host_speed 11.600m 10.001ms 41 50 82.00
V2 speed spi_host_speed 11.600m 10.001ms 41 50 82.00
V2 chip_select_timing spi_host_speed 11.600m 10.001ms 41 50 82.00
V2 sw_reset spi_host_sw_reset 9.467m 15.014ms 40 50 80.00
V2 passthrough_mode spi_host_passthrough_mode 3.000s 439.814us 50 50 100.00
V2 cpol_cpha spi_host_speed 11.600m 10.001ms 41 50 82.00
V2 full_cycle spi_host_speed 11.600m 10.001ms 41 50 82.00
V2 duplex spi_host_smoke 10.217m 49.758ms 39 50 78.00
V2 tx_rx_only spi_host_smoke 10.217m 49.758ms 39 50 78.00
V2 stress_all spi_host_stress_all 18.133m 15.010ms 44 50 88.00
V2 spien spi_host_spien 15.933m 15.001ms 42 50 84.00
V2 stall spi_host_status_stall 8.583m 16.673ms 37 50 74.00
V2 Idlecsbactive spi_host_idlecsbactive 7.400m 10.003ms 35 50 70.00
V2 data_fifo_status spi_host_overflow_underflow 2.283m 11.470ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 18.652us 50 50 100.00
V2 intr_test spi_host_intr_test 5.000s 18.423us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 329.311us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 329.311us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 32.666us 5 5 100.00
spi_host_csr_rw 3.000s 46.818us 20 20 100.00
spi_host_csr_aliasing 3.000s 31.476us 5 5 100.00
spi_host_same_csr_outstanding 4.000s 63.922us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 32.666us 5 5 100.00
spi_host_csr_rw 3.000s 46.818us 20 20 100.00
spi_host_csr_aliasing 3.000s 31.476us 5 5 100.00
spi_host_same_csr_outstanding 4.000s 63.922us 20 20 100.00
V2 TOTAL 629 690 91.16
V2S tl_intg_err spi_host_tl_intg_err 3.000s 90.979us 20 20 100.00
spi_host_sec_cm 3.000s 296.165us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 3.000s 90.979us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 47.950m 100.006ms 2 10 20.00
TOTAL 760 840 90.48

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results