e971cd9798| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 10.217m | 49.758ms | 39 | 50 | 78.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 32.666us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 46.818us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 4.466ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 31.476us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 24.191us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 46.818us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 31.476us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 46.074us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 2.000s | 22.923us | 5 | 5 | 100.00 |
| V1 | TOTAL | 104 | 115 | 90.43 | |||
| V2 | performance | spi_host_performance | 3.000s | 101.690us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.283m | 11.470ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 46.411us | 50 | 50 | 100.00 | ||
| spi_host_event | 28.300m | 75.062ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.600m | 10.001ms | 41 | 50 | 82.00 |
| V2 | speed | spi_host_speed | 11.600m | 10.001ms | 41 | 50 | 82.00 |
| V2 | chip_select_timing | spi_host_speed | 11.600m | 10.001ms | 41 | 50 | 82.00 |
| V2 | sw_reset | spi_host_sw_reset | 9.467m | 15.014ms | 40 | 50 | 80.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 439.814us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.600m | 10.001ms | 41 | 50 | 82.00 |
| V2 | full_cycle | spi_host_speed | 11.600m | 10.001ms | 41 | 50 | 82.00 |
| V2 | duplex | spi_host_smoke | 10.217m | 49.758ms | 39 | 50 | 78.00 |
| V2 | tx_rx_only | spi_host_smoke | 10.217m | 49.758ms | 39 | 50 | 78.00 |
| V2 | stress_all | spi_host_stress_all | 18.133m | 15.010ms | 44 | 50 | 88.00 |
| V2 | spien | spi_host_spien | 15.933m | 15.001ms | 42 | 50 | 84.00 |
| V2 | stall | spi_host_status_stall | 8.583m | 16.673ms | 37 | 50 | 74.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 7.400m | 10.003ms | 35 | 50 | 70.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.283m | 11.470ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 18.652us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 5.000s | 18.423us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 329.311us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 329.311us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 32.666us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 46.818us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 31.476us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 63.922us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 32.666us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 46.818us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 31.476us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 63.922us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 629 | 690 | 91.16 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 90.979us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 296.165us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 90.979us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 47.950m | 100.006ms | 2 | 10 | 20.00 | |
| TOTAL | 760 | 840 | 90.48 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.84 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 18 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
0.spi_host_upper_range_clkdiv.3609558336688746228935023853312606795560712905314353910825912224429810121728
Line 327, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004039410 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe8b53894, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100004039410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_upper_range_clkdiv.106706703081156003762257236121563309604397610559549024913253294903583188823817
Line 337, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002901876 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x46f0bed4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100002901876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 4 failures.
6.spi_host_stress_all.108217153097816697384449320649013001602482205681171041335857471185273645334959
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10004208159 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x41794a94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004208159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_stress_all.84640028504361241024940036602991326775830836291849582095990694432502136872599
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10001916305 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3980a194, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001916305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_smoke has 6 failures.
11.spi_host_smoke.52674714302370130747412261709775994072552569087191427584734121782252711499358
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_smoke/latest/run.log
UVM_FATAL @ 15003721790 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa9d0fc54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15003721790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.spi_host_smoke.30421033080163406446153117224752915474568449764036588946514520032862411408744
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_smoke/latest/run.log
UVM_FATAL @ 15002009938 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb81739d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002009938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_speed has 4 failures.
16.spi_host_speed.64582732116421399336682514458128622240370501250571431124807751564798784169877
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_speed/latest/run.log
UVM_FATAL @ 10001889855 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1483dc14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001889855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_host_speed.82229222702836725619594161572398760868918117830653413099590698136170894705990
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_speed/latest/run.log
UVM_FATAL @ 10003137712 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe2d411d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003137712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_spien has 2 failures.
17.spi_host_spien.102909245119160629897837202328668097672765981692801584174109352294930937149031
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_spien/latest/run.log
UVM_FATAL @ 10001125722 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1e243a94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001125722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.spi_host_spien.104863344048483465913978781434217317773770086547547527160736940755840882068444
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_spien/latest/run.log
UVM_FATAL @ 10000927643 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5c699214, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000927643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 11 failures:
Test spi_host_spien has 4 failures.
0.spi_host_spien.40241044321577857397774489151648443286087085434265452750053131331141972859889
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 10002259045 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xced5a54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002259045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_spien.51868169311745314606966830748290630443625316739209640455607182549583529063255
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_spien/latest/run.log
UVM_FATAL @ 10002236422 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2bab9a14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002236422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_upper_range_clkdiv has 2 failures.
1.spi_host_upper_range_clkdiv.90931887158870582341443558006579146492373246374876014259573781651169224648323
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005778485 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2700394, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100005778485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_upper_range_clkdiv.44288610557326505302152033354636073388672719747197830279443698630817181119484
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004460233 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa7dd1a54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100004460233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 4 failures.
5.spi_host_smoke.47395604916905788165234493284122141304583546656590470382913752460739999397932
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
UVM_FATAL @ 15016058334 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4b578b94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15016058334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_smoke.40056663537675848053777424260649239000509125586813412571014357139681165062728
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
UVM_FATAL @ 15004477197 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5a54cf94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15004477197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_speed has 1 failures.
39.spi_host_speed.512554983404113223133958647447480757280094552490110343363327044643732337496
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_speed/latest/run.log
UVM_FATAL @ 10000884547 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbf9ca914, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000884547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 8 failures:
3.spi_host_idlecsbactive.3636305275184379698337277814581144139347381842548846672711657359607889052999
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004687643 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xeda9ca54, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10004687643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_idlecsbactive.62517162249040999401082296043834195061697449819163906519885333586801831396578
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10010206807 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa5a77814, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10010206807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
8.spi_host_upper_range_clkdiv.75329206912001172454644798153765973542387250696594901359166807392739624505907
Line 329, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003301815 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4c1cb7d4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 100003301815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 4 failures:
19.spi_host_status_stall.70353222865395394234791161288890404405942803167248393164017081266661733526119
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_status_stall/latest/run.log
UVM_ERROR @ 3894028 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 3894028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.spi_host_status_stall.52144189956703923378340095747196629772683117035640198290961334527455439770718
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_status_stall/latest/run.log
UVM_ERROR @ 1611359 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 1611359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 3 failures:
14.spi_host_speed.56794296472649115620231688420700326899093958468134153881155731619453947974093
Line 375, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_speed/latest/run.log
UVM_FATAL @ 10013562403 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x75bd7ad4, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10013562403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_speed.89081413409936315088368505483294478516635698802884768003774975320659853021658
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_speed/latest/run.log
UVM_FATAL @ 10017660885 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x18e38854, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10017660885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 3 failures:
23.spi_host_status_stall.98667969965852420363154002868855556705462973452339640085923239864090231009823
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log
UVM_ERROR @ 14388379 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 14388379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_status_stall.97109882019476072693257933398394541909987820146566745518747972268381955332812
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log
UVM_ERROR @ 19167293 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 19167293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
1.spi_host_sw_reset.552969767153616148511013663384597059414751548831414284090043237124754101758
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003475015 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5506f614, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10003475015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.spi_host_sw_reset.53395082455156229318268429761607661326378169785336082354608079179324298598529
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002550400 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xddf34e14, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10002550400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 2 failures:
Test spi_host_status_stall has 1 failures.
1.spi_host_status_stall.82200845666153880263826437078867412542940776698253361873707314748066194789987
Line 385, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10021210323 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x101c1414, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10021210323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
35.spi_host_spien.49915537097067279726327568203165124817234812647521262865809411911833751477752
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_spien/latest/run.log
UVM_FATAL @ 10200471295 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd5d9eb94, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10200471295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
1.spi_host_idlecsbactive.81138882948272323744543421307294963800925350036652569668781936225688838363119
Line 395, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.spi_host_idlecsbactive.67590881521221017597081571083224368373976901330872515227210606093916424724890
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
2.spi_host_upper_range_clkdiv.60320907859496425356405691125388657896731254820388410886519727415855441884640
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:25a19e20-2a29-4bb5-a2fd-0923250b64fc
4.spi_host_upper_range_clkdiv.57791501193302131941865268545949961652769263553567073071914290392741554439579
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:cd0bcb55-8c2d-4d5e-8bde-322dfe1da01a
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 2 failures:
2.spi_host_idlecsbactive.71482112395632821347277729261146327379276121939473847786078384856819829365178
Line 327, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10005407538 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xeff01c94, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10005407538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.spi_host_idlecsbactive.77629255575611275288940734647852648519540208440706703866603559713712034414008
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10025491214 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbfcce254, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10025491214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 2 failures:
Test spi_host_speed has 1 failures.
3.spi_host_speed.98972724824829303685847695601046170155779050895919848934573611607692609441841
Line 375, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_speed/latest/run.log
UVM_FATAL @ 10022660934 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9d5e2754, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10022660934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
30.spi_host_spien.12902652005924814165262522971835122976565764223961744852864849507816146562491
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_spien/latest/run.log
UVM_FATAL @ 10038706374 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb0628c14, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10038706374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
17.spi_host_idlecsbactive.86379852262057163050068593068680008906298693534934743908958030719387282483924
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002521407 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x78f01c54, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10002521407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_idlecsbactive.99060762096634331975294901100311654206019497636585324083313873798783391027076
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004506272 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x92377714, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10004506272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
24.spi_host_sw_reset.38687008500821645933464118784603626827283787630633832128870354199444151397343
Line 348, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002747480 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcbfe0b54, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10002747480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_host_sw_reset.107257906275105292840950314718171143960826568166929161681081765400044712346892
Line 340, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15014241912 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x66fa7e54, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 15014241912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
38.spi_host_idlecsbactive.104043225744985001116114098324523225592514895482668560044612724142872389188472
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10012699936 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9a868914, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10012699936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.spi_host_idlecsbactive.20008159402376897425853676615445747275936588884101757851967354428875298412598
Line 331, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10008793734 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x168bab94, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10008793734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
2.spi_host_status_stall.40762844991317850909765625037600064980607832715115808352241753268838901348223
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10001502345 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf5018fd4, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10001502345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
3.spi_host_upper_range_clkdiv.37655445386848062431161881323044225028006486277567078376844311970831727135944
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100015186981 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc244b514, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 100015186981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=32) has 1 failures:
3.spi_host_sw_reset.22399054373941812286320044997609899876227940155024242684257113952575139745038
Line 442, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10021169936 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x54cbbb94, Comparison=CompareOpEq, exp_data=0x0, call_count=32)
UVM_INFO @ 10021169936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
7.spi_host_status_stall.72835709904504337642780792351179440317316996151245070101816687612870719378481
Line 409, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15179504277 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5025c614, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 15179504277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=60) has 1 failures:
7.spi_host_stress_all.25162638349166667404996119810404122062493738614695830635050937449730503387079
Line 536, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_stress_all/latest/run.log
UVM_FATAL @ 16515314963 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x50a2d394, Comparison=CompareOpEq, exp_data=0x1, call_count=60)
UVM_INFO @ 16515314963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=178) has 1 failures:
8.spi_host_status_stall.62598216692511045762459457984299177232891721697209759466002786366998174577635
Line 1094, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15336937228 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x22c93d54, Comparison=CompareOpEq, exp_data=0x0, call_count=178)
UVM_INFO @ 15336937228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
9.spi_host_sw_reset.38252784499650104417439658735380876028370107292550662669619931843448354345795
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003535501 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb1149ad4, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10003535501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
10.spi_host_sw_reset.47634439450443274386935024718837069285551897206755037724381044769879274718755
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003315962 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb8e27154, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10003315962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=85) has 1 failures:
11.spi_host_status_stall.114789544744522255282708102171677263080388556379386638903183600850193672554012
Line 933, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_FATAL @ 46121505179 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x68b94d14, Comparison=CompareOpEq, exp_data=0x1, call_count=85)
UVM_INFO @ 46121505179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
25.spi_host_smoke.57398912393193014037914310945733992819727297854003871415494362482798179069209
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_smoke/latest/run.log
UVM_FATAL @ 10013173109 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5a77da14, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 10013173109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
25.spi_host_sw_reset.86458939774839458267110278577389635623332425851681986448045130178231847328331
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10026182013 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x70a389d4, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10026182013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
32.spi_host_sw_reset.78175500139549031259809146412884753623209945532666406101380385374295402216484
Line 375, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10096269957 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x92582ad4, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10096269957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
39.spi_host_status_stall.38623573288646700883517660518431439234129613148287865670094527770690668089366
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10004143000 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb2cf9694, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10004143000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
42.spi_host_sw_reset.6650397341965631087760657120794912107672220068561281378125696315466371359590
Line 336, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15021675053 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x274f7a54, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 15021675053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
45.spi_host_stress_all.78220814719556231720179947416045759169123820632314276329007217835149986256108
Line 426, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15009713642 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x44e58c54, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 15009713642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---