SPI_HOST Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 17.300m 15.001ms 40 50 80.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 20.490us 5 5 100.00
V1 csr_rw spi_host_csr_rw 12.000s 21.519us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 9.000s 194.586us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 12.000s 29.473us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 8.000s 28.097us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 12.000s 21.519us 20 20 100.00
spi_host_csr_aliasing 12.000s 29.473us 5 5 100.00
V1 mem_walk spi_host_mem_walk 12.000s 24.432us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 59.557us 5 5 100.00
V1 TOTAL 105 115 91.30
V2 performance spi_host_performance 13.000s 100.668us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.200m 2.955ms 50 50 100.00
spi_host_error_cmd 7.000s 31.151us 50 50 100.00
spi_host_event 13.967m 126.886ms 50 50 100.00
V2 clock_rate spi_host_speed 11.667m 10.001ms 38 50 76.00
V2 speed spi_host_speed 11.667m 10.001ms 38 50 76.00
V2 chip_select_timing spi_host_speed 11.667m 10.001ms 38 50 76.00
V2 sw_reset spi_host_sw_reset 9.533m 15.006ms 42 50 84.00
V2 passthrough_mode spi_host_passthrough_mode 8.000s 218.499us 50 50 100.00
V2 cpol_cpha spi_host_speed 11.667m 10.001ms 38 50 76.00
V2 full_cycle spi_host_speed 11.667m 10.001ms 38 50 76.00
V2 duplex spi_host_smoke 17.300m 15.001ms 40 50 80.00
V2 tx_rx_only spi_host_smoke 17.300m 15.001ms 40 50 80.00
V2 stress_all spi_host_stress_all 7.950m 15.002ms 46 50 92.00
V2 spien spi_host_spien 7.800m 15.003ms 41 50 82.00
V2 stall spi_host_status_stall 4.833m 27.310ms 31 50 62.00
V2 Idlecsbactive spi_host_idlecsbactive 8.217m 200.000ms 42 50 84.00
V2 data_fifo_status spi_host_overflow_underflow 2.200m 2.955ms 50 50 100.00
V2 alert_test spi_host_alert_test 7.000s 42.812us 50 50 100.00
V2 intr_test spi_host_intr_test 17.000s 119.580us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 14.000s 172.047us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 14.000s 172.047us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 20.490us 5 5 100.00
spi_host_csr_rw 12.000s 21.519us 20 20 100.00
spi_host_csr_aliasing 12.000s 29.473us 5 5 100.00
spi_host_same_csr_outstanding 12.000s 270.862us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 20.490us 5 5 100.00
spi_host_csr_rw 12.000s 21.519us 20 20 100.00
spi_host_csr_aliasing 12.000s 29.473us 5 5 100.00
spi_host_same_csr_outstanding 12.000s 270.862us 20 20 100.00
V2 TOTAL 630 690 91.30
V2S tl_intg_err spi_host_tl_intg_err 5.000s 341.809us 20 20 100.00
spi_host_sec_cm 3.000s 140.128us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 5.000s 341.809us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 57.467m 100.001ms 4 10 40.00
TOTAL 764 840 90.95

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
90.99 90.92 83.18 92.77 89.61 95.70 100.00 95.07 90.87

Failure Buckets

Past Results