e971cd9798| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 17.300m | 15.001ms | 40 | 50 | 80.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 4.000s | 20.490us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 12.000s | 21.519us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 9.000s | 194.586us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 12.000s | 29.473us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 8.000s | 28.097us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 12.000s | 21.519us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 12.000s | 29.473us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 12.000s | 24.432us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 59.557us | 5 | 5 | 100.00 |
| V1 | TOTAL | 105 | 115 | 91.30 | |||
| V2 | performance | spi_host_performance | 13.000s | 100.668us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.200m | 2.955ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 7.000s | 31.151us | 50 | 50 | 100.00 | ||
| spi_host_event | 13.967m | 126.886ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.667m | 10.001ms | 38 | 50 | 76.00 |
| V2 | speed | spi_host_speed | 11.667m | 10.001ms | 38 | 50 | 76.00 |
| V2 | chip_select_timing | spi_host_speed | 11.667m | 10.001ms | 38 | 50 | 76.00 |
| V2 | sw_reset | spi_host_sw_reset | 9.533m | 15.006ms | 42 | 50 | 84.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 8.000s | 218.499us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.667m | 10.001ms | 38 | 50 | 76.00 |
| V2 | full_cycle | spi_host_speed | 11.667m | 10.001ms | 38 | 50 | 76.00 |
| V2 | duplex | spi_host_smoke | 17.300m | 15.001ms | 40 | 50 | 80.00 |
| V2 | tx_rx_only | spi_host_smoke | 17.300m | 15.001ms | 40 | 50 | 80.00 |
| V2 | stress_all | spi_host_stress_all | 7.950m | 15.002ms | 46 | 50 | 92.00 |
| V2 | spien | spi_host_spien | 7.800m | 15.003ms | 41 | 50 | 82.00 |
| V2 | stall | spi_host_status_stall | 4.833m | 27.310ms | 31 | 50 | 62.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 8.217m | 200.000ms | 42 | 50 | 84.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.200m | 2.955ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 7.000s | 42.812us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 17.000s | 119.580us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 14.000s | 172.047us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 14.000s | 172.047us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 4.000s | 20.490us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 12.000s | 21.519us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 12.000s | 29.473us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 12.000s | 270.862us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 4.000s | 20.490us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 12.000s | 21.519us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 12.000s | 29.473us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 12.000s | 270.862us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 630 | 690 | 91.30 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 5.000s | 341.809us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 140.128us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 5.000s | 341.809us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 57.467m | 100.001ms | 4 | 10 | 40.00 | |
| TOTAL | 764 | 840 | 90.95 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 90.99 | 90.92 | 83.18 | 92.77 | 89.61 | 95.70 | 100.00 | 95.07 | 90.87 |
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 13 failures:
Test spi_host_spien has 4 failures.
0.spi_host_spien.29112455952979245862476049032205843619365763399197845419672775579438902195196
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 10002073964 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x92dbf414, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002073964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_spien.112331260959624565119600680363518459257170528099499532709922975780828482560456
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_spien/latest/run.log
UVM_FATAL @ 10004481676 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb9488354, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004481676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_speed has 5 failures.
2.spi_host_speed.50443297637617894591015139137540364650531816759142725869365690106904967052344
Line 371, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_speed/latest/run.log
UVM_FATAL @ 10004768966 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe8bb5b94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004768966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_speed.56090988095459867082667688995065847763867145045678620715426846814294023490739
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_speed/latest/run.log
UVM_FATAL @ 10001104371 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5707dad4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001104371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_upper_range_clkdiv has 1 failures.
2.spi_host_upper_range_clkdiv.42881789237998204154550174763032507175378211917949173466660472649394088847265
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100000738503 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe3e27214, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100000738503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 3 failures.
10.spi_host_smoke.114030950507447277030182514771532815055734136595931197704071636608762168509939
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
UVM_FATAL @ 15005981025 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x33fd0bd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15005981025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_host_smoke.5637899024480227234167590551240043412427752364169019110161351896131576884727
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001516738 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb84bbb14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001516738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 13 failures:
Test spi_host_upper_range_clkdiv has 3 failures.
3.spi_host_upper_range_clkdiv.114054759815784734534790631603998710629327640712537605389313663794295811405383
Line 327, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100011188748 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb76e10d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100011188748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_upper_range_clkdiv.114089968503691303569975393903427244475870295074655946898792994698370940572810
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005732114 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x61901694, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100005732114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_speed has 2 failures.
6.spi_host_speed.11789789034558603386519953586344053877128923168581738103520090094993955974028
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/latest/run.log
UVM_FATAL @ 10000941818 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x18d97354, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000941818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.spi_host_speed.39719965833253971338170712113365774624172885213698652880422361156972857840195
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_speed/latest/run.log
UVM_FATAL @ 10000795041 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9480ba54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000795041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 3 failures.
10.spi_host_stress_all.73033159766614824559541461823713821434806636459296665464749065132131952778266
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15002094534 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa0fd0654, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002094534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_host_stress_all.86661141738078053843958665497501013295951924120421200707038994730841365365504
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15036527803 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x32bdb594, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15036527803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_spien has 1 failures.
10.spi_host_spien.73756093735657004963022292591405049925753848637169981019860450522440825218904
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_spien/latest/run.log
UVM_FATAL @ 10003419576 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb504bcd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003419576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 4 failures.
16.spi_host_smoke.44608092053186110981480396263546307622674526580909686390905366843318878822799
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_smoke/latest/run.log
UVM_FATAL @ 15002214474 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3c81eb54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002214474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_smoke.90656462758375954865827043298021379385425757185973916842988806669405421952519
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000800130 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3729c754, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000800130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 6 failures:
22.spi_host_status_stall.68548912093374232854985029250409701099126758026770432646258219517732132583046
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
UVM_ERROR @ 6542628 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6542628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_host_status_stall.73051310374711780826064346947016762664364578142702813512620390870954795417491
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_status_stall/latest/run.log
UVM_ERROR @ 2541958 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2541958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 4 failures:
1.spi_host_status_stall.95653232676635728780028468206557348286077543620602658781936988961083884645004
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10004510534 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x99d7d414, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10004510534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_host_status_stall.84981613282437701068787567563031526283116655053093483981348143075508033131513
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003445688 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x62ff1454, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10003445688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 4 failures:
Test spi_host_sw_reset has 2 failures.
16.spi_host_sw_reset.80806429793902212431432618206876360951847516801460291748920461685345044515164
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10013098264 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xec0b3614, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10013098264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.spi_host_sw_reset.31390070909157235460956670242463226523846373144292452433303108490999818946993
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15003046808 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xba38cf54, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 15003046808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
27.spi_host_spien.93878401302055479205720384109874084354060658736871921258181374838879050478977
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_spien/latest/run.log
UVM_FATAL @ 10007434946 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x38bf2494, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10007434946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
38.spi_host_status_stall.70375197332596763165059458408168710241384437040615521825991908490819168110391
Line 371, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10059670597 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6e7713d4, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10059670597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 3 failures:
Test spi_host_smoke has 2 failures.
0.spi_host_smoke.44055989873934494429964477470262742338034377123100350154188253574148331437828
Line 371, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
UVM_FATAL @ 15193926945 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x97c3bb14, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 15193926945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.spi_host_smoke.59733142181961420804718246943763467959559630109823996663922720932766528169539
Line 367, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_smoke/latest/run.log
UVM_FATAL @ 15147677287 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3a2db994, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 15147677287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
41.spi_host_status_stall.101482166267386927327756406336352289209105586098489994293681047723728632398777
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10023286393 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4bfab814, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10023286393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 3 failures:
12.spi_host_idlecsbactive.41216500522739195434241750844466198158724680737709344643402456653454469100783
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002450942 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6f305594, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10002450942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_host_idlecsbactive.19350794915357890978727408544323910399623131881152478997226613114904423789587
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10015735721 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x70ba4ad4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10015735721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 2 failures:
2.spi_host_status_stall.67825787954351176271308901633711038330262668555821936609988717886886769717796
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_ERROR @ 4070219 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 4070219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_status_stall.76101233146827149634092510871289691668498413261037898586553946863930839650537
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_status_stall/latest/run.log
UVM_ERROR @ 12594577 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 12594577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
5.spi_host_status_stall.68993685793936155623432077815558949371665811464486869134035574739758342884672
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15004150689 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xefc052d4, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 15004150689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.spi_host_status_stall.41566199139760673646738446274048330398812005421356511325180171419387407950258
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10005857823 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x574ae894, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10005857823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
7.spi_host_upper_range_clkdiv.37266520392142344040034634614287715246415275915628363371348251938263767364542
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:a1234b0a-ebbc-451f-8bb9-6227a477b772
8.spi_host_upper_range_clkdiv.91887374409492064201905748085168463824455469657373939356560886342864162095762
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:472f7634-b454-4b7b-9dfc-86c7d9ea31f4
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
7.spi_host_sw_reset.81892665289685417681843717203389437090953608182181794267388950682009105250023
Line 340, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10004426074 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe8032094, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10004426074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.spi_host_sw_reset.99455548857052124811607284891102901376884024862938842092676026207940614185984
Line 322, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15059531471 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfe845554, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15059531471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
7.spi_host_idlecsbactive.94869113886733914503849540803886460563298502135146303526263506061144466090406
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10003747732 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x49708454, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10003747732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.spi_host_idlecsbactive.97742747037418865935855468155824293902633411391745607263752261907695817751207
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10003481411 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf1b88d4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10003481411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=36) has 1 failures:
2.spi_host_sw_reset.101692164009224042565384789145573170952473817449943213489724700846054712744376
Line 451, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10341201619 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x461385d4, Comparison=CompareOpEq, exp_data=0x0, call_count=36)
UVM_INFO @ 10341201619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=28) has 1 failures:
6.spi_host_spien.45639938159482546457098891707818020296197673739522272397057941540537303751571
Line 459, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_spien/latest/run.log
UVM_FATAL @ 10011973928 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x700fd6d4, Comparison=CompareOpEq, exp_data=0x1, call_count=28)
UVM_INFO @ 10011973928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
7.spi_host_status_stall.57685529063012427886394872363961979208167704610543904104981481899706272542213
Line 371, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10022723293 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6f656954, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10022723293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
8.spi_host_status_stall.36416456955098736315956423693118414714865560443190446961564965862980956223440
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10005084157 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9b63e114, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10005084157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
9.spi_host_sw_reset.92517540372854403954199978643345849183237883209084036223281507719213936940934
Line 340, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15006348415 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x85a576d4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 15006348415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
10.spi_host_idlecsbactive.54745436963313877353945108056582766474129625957467449498966791131210260875124
Line 403, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
11.spi_host_speed.92438130875339944501667039909139308663551632132571187290437845945854085937314
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_speed/latest/run.log
UVM_FATAL @ 10011599218 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x780ed314, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10011599218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
12.spi_host_smoke.72137532773852382465590036060243507263696063441849110458453196846720293674985
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_smoke/latest/run.log
UVM_FATAL @ 15791486167 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3bf04e14, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 15791486167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=33) has 1 failures:
14.spi_host_speed.18545647373341717120581996332895113087869064998753210191625722509328311897141
Line 417, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_speed/latest/run.log
UVM_FATAL @ 10024616830 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x88133c94, Comparison=CompareOpEq, exp_data=0x1, call_count=33)
UVM_INFO @ 10024616830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
16.spi_host_speed.43813819468631195516877127929954062175579141980975449840177175011110453719226
Line 387, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_speed/latest/run.log
UVM_FATAL @ 10025395193 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf12cb254, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
UVM_INFO @ 10025395193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=46) has 1 failures:
16.spi_host_spien.42814583671446527438557234170966389592355375303206049882293910666192066925680
Line 507, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_spien/latest/run.log
UVM_FATAL @ 10102114629 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6e7d7bd4, Comparison=CompareOpEq, exp_data=0x1, call_count=46)
UVM_INFO @ 10102114629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=47) has 1 failures:
21.spi_host_sw_reset.31373514761761233658277555806713087909388121180901659804313799079838534126278
Line 506, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10061536208 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf91c5814, Comparison=CompareOpEq, exp_data=0x1, call_count=47)
UVM_INFO @ 10061536208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
26.spi_host_sw_reset.56380265163555126897919815459384557658752977613370650698728247703407119431778
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10037471923 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x61cbe994, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10037471923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
29.spi_host_speed.31543391603774471021007609893779739041918557529749868915294473916656347318444
Line 403, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_speed/latest/run.log
UVM_FATAL @ 10053968885 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xafe35014, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
UVM_INFO @ 10053968885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=93) has 1 failures:
31.spi_host_status_stall.92982477769004458288179130420241417469051772872667568945534942798112697209182
Line 973, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log
UVM_FATAL @ 12427093266 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf1bdfc14, Comparison=CompareOpEq, exp_data=0x1, call_count=93)
UVM_INFO @ 12427093266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
34.spi_host_stress_all.44687706964482012641864893727886039551694575112793230095831278151304374049494
Line 434, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10027883959 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x394fac14, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10027883959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
44.spi_host_speed.40731914740129454461392221948537783583371385149416305870924765089375136164383
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_speed/latest/run.log
UVM_FATAL @ 10024001919 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x32cea354, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10024001919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
46.spi_host_idlecsbactive.5561022009615704412880500930947917337727551399134960759583505324099648395843
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10029427896 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xff926c14, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10029427896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
47.spi_host_idlecsbactive.56604890531407830066620716540427143656400668700679223537249785625861946361654
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10003345226 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x50b96b94, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10003345226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=34) has 1 failures:
48.spi_host_spien.105779946448581148967039681114737758919928138948985160920490635101156440935565
Line 439, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_spien/latest/run.log
UVM_FATAL @ 25857515028 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd41688d4, Comparison=CompareOpEq, exp_data=0x1, call_count=34)
UVM_INFO @ 25857515028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---