e971cd9798| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 12.583m | 15.001ms | 38 | 50 | 76.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 18.987us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 20.923us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 4.000s | 330.093us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 103.918us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 36.616us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 20.923us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 103.918us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 16.005us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 16.465us | 5 | 5 | 100.00 |
| V1 | TOTAL | 103 | 115 | 89.57 | |||
| V2 | performance | spi_host_performance | 12.000s | 33.979us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.800m | 13.109ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 7.000s | 49.826us | 50 | 50 | 100.00 | ||
| spi_host_event | 18.700m | 70.216ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.300m | 10.001ms | 36 | 50 | 72.00 |
| V2 | speed | spi_host_speed | 11.300m | 10.001ms | 36 | 50 | 72.00 |
| V2 | chip_select_timing | spi_host_speed | 11.300m | 10.001ms | 36 | 50 | 72.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.033m | 16.572ms | 42 | 50 | 84.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 675.415us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.300m | 10.001ms | 36 | 50 | 72.00 |
| V2 | full_cycle | spi_host_speed | 11.300m | 10.001ms | 36 | 50 | 72.00 |
| V2 | duplex | spi_host_smoke | 12.583m | 15.001ms | 38 | 50 | 76.00 |
| V2 | tx_rx_only | spi_host_smoke | 12.583m | 15.001ms | 38 | 50 | 76.00 |
| V2 | stress_all | spi_host_stress_all | 25.883m | 22.512ms | 41 | 50 | 82.00 |
| V2 | spien | spi_host_spien | 5.633m | 10.001ms | 38 | 50 | 76.00 |
| V2 | stall | spi_host_status_stall | 7.683m | 10.002ms | 35 | 50 | 70.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 12.767m | 200.000ms | 31 | 50 | 62.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.800m | 13.109ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 7.000s | 18.696us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 32.494us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 42.842us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 42.842us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 18.987us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 20.923us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 103.918us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 23.684us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 18.987us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 20.923us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 103.918us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 23.684us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 613 | 690 | 88.84 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 196.521us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 2.000s | 348.872us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 196.521us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 47.717m | 100.005ms | 2 | 10 | 20.00 | |
| TOTAL | 743 | 840 | 88.45 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.84 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 24 failures:
0.spi_host_stress_all.113607401839929250149064750954245399414232417569766520272826459589685389933407
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001213238 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7d640cd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001213238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_stress_all.72238283403373578719513839723299223888647687353559035520215527362019372619084
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15000805007 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd1ab4e14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000805007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
1.spi_host_upper_range_clkdiv.100398691285909923372127068987269817626272502849554356269212511875730444695022
Line 317, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100007275193 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe36b54d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100007275193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_upper_range_clkdiv.54903989531477460444422580982500033464368050269288741433083027476627182017497
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100001596819 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd11b3e54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100001596819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
1.spi_host_spien.85041247002524595602810938433325111155301739301556616114795114477189839599788
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_spien/latest/run.log
UVM_FATAL @ 10001079019 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8826da94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001079019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_host_spien.79708256190431715265966975887338416643804283267746648262175691926406831659914
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_spien/latest/run.log
UVM_FATAL @ 10002283943 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x58f9d994, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002283943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
2.spi_host_smoke.97007003777654734846403101075222575158903050111454738819922460374364076786309
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_smoke/latest/run.log
UVM_FATAL @ 15002952878 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xeea30794, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002952878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.spi_host_smoke.86220336814209052954381175803448904069751157731978868119074874129936700023066
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_smoke/latest/run.log
UVM_FATAL @ 15002572907 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xef8c81d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002572907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
12.spi_host_speed.45872872353296947750948072438952369721931094564325254669590435232280963129672
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_speed/latest/run.log
UVM_FATAL @ 10003676907 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x973a0b54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003676907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_host_speed.99055089958747452959327960754263320495853385810924708475062759591773835797908
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_speed/latest/run.log
UVM_FATAL @ 10004860506 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc9cde6d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004860506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 11 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
5.spi_host_upper_range_clkdiv.30946097200660473321115968485999299765224062950238325075736392625588164240806
Line 325, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005263119 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb2a60b14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100005263119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_upper_range_clkdiv.64114713589103267784091399713874185514648047506856292143981609131839671766563
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003228549 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2c0d7414, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003228549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 4 failures.
15.spi_host_smoke.24139765606967149789408630439803652688404872624118454653185728679261613175767
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_smoke/latest/run.log
UVM_FATAL @ 15007537140 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1dfb2ad4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15007537140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.spi_host_smoke.108435595653744603230503957548816836232097033812490002337826642947357858514418
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000892381 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcd2a8b14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000892381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_speed has 4 failures.
21.spi_host_speed.100795451933471420448869564945860241766601119591957481672642602798579075584020
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_speed/latest/run.log
UVM_FATAL @ 10002691831 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd9fb1154, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002691831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_speed.107376141705001286224972231317708573224572326663494851291077454834777194382111
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_speed/latest/run.log
UVM_FATAL @ 10001520210 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x50d8414, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001520210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_spien has 1 failures.
34.spi_host_spien.14758599955860334502914232033859876865516496290194915242545027484442730148947
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_spien/latest/run.log
UVM_FATAL @ 10003908299 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7af2bb94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003908299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 6 failures:
4.spi_host_idlecsbactive.3514265739086813595930166860425098180151966935106984801861721135487979462465
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10014389434 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x574b7154, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10014389434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.spi_host_idlecsbactive.56708968663332947336434739260523800577994621138187776274113331950188168207176
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002755646 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x39674a54, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10002755646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 5 failures:
2.spi_host_idlecsbactive.93600517125847944740092655860197365495953858455475670151532326651261299543082
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004008262 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x85de8914, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10004008262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_idlecsbactive.77920153760861680810105158550316225271199592473533192527072906219405304517054
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002609045 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xad569b14, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10002609045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 5 failures:
14.spi_host_idlecsbactive.92863491599778128289269790852208133365061134267834325120276041134905813918799
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10018324080 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe15c3054, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10018324080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_idlecsbactive.74340566333334589147325579645373628923690494422342397075892330252506606803776
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15009639419 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xef62394, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 15009639419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 3 failures:
2.spi_host_status_stall.59507652491463802516620937343919788123605493796089860500615657002830005935456
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003638192 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2970bfd4, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10003638192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.spi_host_status_stall.44709168695703875058692034444255249882441850737876643180008041086478214725784
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10002997893 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf8118614, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10002997893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test spi_host_upper_range_clkdiv has 1 failures.
3.spi_host_upper_range_clkdiv.10175280569316207926548649415755275564089446119919603301051761558367174774230
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_idlecsbactive has 2 failures.
29.spi_host_idlecsbactive.56425232021218730234795722859751417898361547481591827455081934133896929355511
Line 411, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_host_idlecsbactive.72008152589381062471400317723569933769752417973108879531686468720350290719128
Line 403, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 2 failures:
Test spi_host_spien has 1 failures.
2.spi_host_spien.79611968152938857728217700308941233617388230034059710119965231741088871923478
Line 379, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_spien/latest/run.log
UVM_FATAL @ 15254400707 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x83a7de54, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 15254400707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
32.spi_host_speed.106974927833291747214878651789221240206432250194697507140211008702468197308899
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_speed/latest/run.log
UVM_FATAL @ 10009619904 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf9f20494, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 10009619904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 2 failures:
7.spi_host_stress_all.89070496829323505797560523310839963877980713156083893830337391878776720068839
Line 422, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22511971774 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb85da314, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 22511971774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.spi_host_stress_all.104874942249547998257064313736936404069874724966388151252404284246690103190378
Line 410, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10023885276 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x99b948d4, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10023885276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 2 failures:
8.spi_host_stress_all.101563530081256810993531089718893071711257878477928545148917505646221022734321
Line 414, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15012137031 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc6b3d654, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 15012137031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_host_stress_all.4181303688923624198882545589521409003187273176173930912615065309604848839754
Line 386, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15041362123 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcf01c414, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 15041362123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 2 failures:
11.spi_host_status_stall.113696418382602869279438581137305164140549472492498337863509943733766440129394
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_ERROR @ 5179638 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 5179638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_host_status_stall.1169259745667299315596005402372463085873465132542863654435230523223766191716
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
UVM_ERROR @ 1528877 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 1528877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 2 failures:
Test spi_host_spien has 1 failures.
22.spi_host_spien.28014598970774895791756842098716114007289961920872073964477764905957599921625
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_spien/latest/run.log
UVM_FATAL @ 10012419249 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf5ef54, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10012419249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
39.spi_host_status_stall.22428714943654881442958413219458894035465529974475860383794556001707671808442
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10051768909 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xafa57bd4, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10051768909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
0.spi_host_upper_range_clkdiv.85522050144198917486726388352396037318483122387671981263062155167351712594745
Line 323, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005030637 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x69d59754, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 100005030637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
3.spi_host_status_stall.110365066439080079014923872938808440154229867074376626884386626048154713731452
Line 413, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10034002677 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8af64d14, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10034002677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=33) has 1 failures:
3.spi_host_spien.114878558573360327560593873624003088505419028448666028711019153102850016056531
Line 431, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_spien/latest/run.log
UVM_FATAL @ 10374980151 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf4a56794, Comparison=CompareOpEq, exp_data=0x1, call_count=33)
UVM_INFO @ 10374980151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
4.spi_host_smoke.110322392452198911834503799640809890472436953751448752571938564752634464153594
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
UVM_FATAL @ 15080233928 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb9ee5854, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
UVM_INFO @ 15080233928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
4.spi_host_status_stall.58207704157877759391697792787765554879525146590852579415766467687815787055784
Line 455, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log
UVM_FATAL @ 17719789258 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x99cde014, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
UVM_INFO @ 17719789258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
7.spi_host_spien.110913360715871182006922360921292752335774798700244109289342056205874697700119
Line 389, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_spien/latest/run.log
UVM_FATAL @ 10009550158 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x14dc4814, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 10009550158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
8.spi_host_smoke.1989831109812846023569272507709195157203834754798094484680284281701660959940
Line 389, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_smoke/latest/run.log
UVM_FATAL @ 10083862954 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x959966d4, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10083862954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
8.spi_host_upper_range_clkdiv.115780411819638030494062726190429252838312911129712599514153330963929216746633
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004265479 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x8942e314, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 100004265479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
9.spi_host_status_stall.10786199148733431223282961532277018182741418155209192554893208376142990662174
Line 493, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
UVM_FATAL @ 21060155579 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xed66e614, Comparison=CompareOpEq, exp_data=0x1, call_count=30)
UVM_INFO @ 21060155579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
11.spi_host_speed.64060465733857954987330396639890189935514455101997873923340587004909357262239
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_speed/latest/run.log
UVM_FATAL @ 10005020560 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x52d20314, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10005020560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
11.spi_host_sw_reset.114641171088266121498588513865906903715513441507374794548964481193829215551521
Line 386, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10228046211 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9a61d694, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 10228046211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
11.spi_host_spien.42677782555614783212802451275706061339610209349631555032856408963061267165432
Line 367, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_spien/latest/run.log
UVM_FATAL @ 10014856499 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfbea2ad4, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10014856499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
12.spi_host_sw_reset.80566888993976512814608047998858277447399139954718944155440816323895328652731
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10004227967 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb3da1054, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10004227967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
17.spi_host_sw_reset.20783176129249472378793133341472871272218288904728411263316925592655955756414
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15008421550 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcf5be294, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 15008421550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
18.spi_host_sw_reset.69944937511222091448766146380242689047017828777207074019063626707774275618998
Line 334, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002786080 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfc0f3d54, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10002786080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
23.spi_host_spien.74571991955392483253059479130484232652990400753515074619967533454518277240855
Line 409, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_spien/latest/run.log
UVM_FATAL @ 10019479518 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x26b06594, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
UVM_INFO @ 10019479518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
26.spi_host_status_stall.97170734029161097475328449899465306360847235073958182896278991829238923369992
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10002072799 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xca929814, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10002072799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=79) has 1 failures:
27.spi_host_status_stall.40390056896287581552370256729514492926552936518108887689956503032817046847414
Line 911, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
UVM_FATAL @ 11752655405 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x38a44d54, Comparison=CompareOpEq, exp_data=0x1, call_count=79)
UVM_INFO @ 11752655405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
28.spi_host_status_stall.28639856176884702823968268188569275359577572300478289416851220859435279892145
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10001708581 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfde1b454, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10001708581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:
29.spi_host_status_stall.97669353410461275231092922157357462502951410986799642677359870418791499603399
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
UVM_ERROR @ 15330909 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 15330909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
30.spi_host_sw_reset.37827422951360218331362659824887498966250287694021557082585142968641718866407
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 16572472598 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4228314, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 16572472598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
36.spi_host_sw_reset.48830061287554210076066028434139339198473742929329561917857234240904922698982
Line 429, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15197080621 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd7033314, Comparison=CompareOpEq, exp_data=0x1, call_count=30)
UVM_INFO @ 15197080621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
37.spi_host_stress_all.6398944513184646844072615854323533797823445574923486225522410262314797369664
Line 447, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10068730848 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfa6d2254, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10068730848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=31) has 1 failures:
41.spi_host_speed.40782904931726311821209568327992588561020534272581451283337847975005493587283
Line 425, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_speed/latest/run.log
UVM_FATAL @ 10077790955 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x17773c14, Comparison=CompareOpEq, exp_data=0x1, call_count=31)
UVM_INFO @ 10077790955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=84) has 1 failures:
41.spi_host_status_stall.17796352746549800162981801015666912907449218315296993979710601559712519327533
Line 921, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
UVM_FATAL @ 13500807390 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfe6aa894, Comparison=CompareOpEq, exp_data=0x1, call_count=84)
UVM_INFO @ 13500807390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
41.spi_host_idlecsbactive.52228232699806914894365600339139063682873887038425621615988470348877486193028
Line 331, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004087109 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x87a7c6d4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10004087109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
41.spi_host_spien.32581145936757426434030072022379062694516553947267519893648436538247538217734
Line 397, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_spien/latest/run.log
UVM_FATAL @ 10013891512 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2c5f4894, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
UVM_INFO @ 10013891512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
43.spi_host_status_stall.46381226963875529406443192724912739132732218506992087499272066429308342341805
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10015019257 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5bbae414, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10015019257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
44.spi_host_sw_reset.30968324633750422804121162861928060315537594428535588201296756458219532225963
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10011463123 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf78db6d4, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10011463123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
46.spi_host_sw_reset.31447708891576366184290769077227335695966621285212864663905815217432969606788
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10010546039 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7f98ea14, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10010546039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---