SPI_HOST Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 12.583m 15.001ms 38 50 76.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 18.987us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 20.923us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 330.093us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 103.918us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 36.616us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 20.923us 20 20 100.00
spi_host_csr_aliasing 3.000s 103.918us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 16.005us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 16.465us 5 5 100.00
V1 TOTAL 103 115 89.57
V2 performance spi_host_performance 12.000s 33.979us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.800m 13.109ms 50 50 100.00
spi_host_error_cmd 7.000s 49.826us 50 50 100.00
spi_host_event 18.700m 70.216ms 50 50 100.00
V2 clock_rate spi_host_speed 11.300m 10.001ms 36 50 72.00
V2 speed spi_host_speed 11.300m 10.001ms 36 50 72.00
V2 chip_select_timing spi_host_speed 11.300m 10.001ms 36 50 72.00
V2 sw_reset spi_host_sw_reset 10.033m 16.572ms 42 50 84.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 675.415us 50 50 100.00
V2 cpol_cpha spi_host_speed 11.300m 10.001ms 36 50 72.00
V2 full_cycle spi_host_speed 11.300m 10.001ms 36 50 72.00
V2 duplex spi_host_smoke 12.583m 15.001ms 38 50 76.00
V2 tx_rx_only spi_host_smoke 12.583m 15.001ms 38 50 76.00
V2 stress_all spi_host_stress_all 25.883m 22.512ms 41 50 82.00
V2 spien spi_host_spien 5.633m 10.001ms 38 50 76.00
V2 stall spi_host_status_stall 7.683m 10.002ms 35 50 70.00
V2 Idlecsbactive spi_host_idlecsbactive 12.767m 200.000ms 31 50 62.00
V2 data_fifo_status spi_host_overflow_underflow 2.800m 13.109ms 50 50 100.00
V2 alert_test spi_host_alert_test 7.000s 18.696us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 32.494us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 42.842us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 42.842us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 18.987us 5 5 100.00
spi_host_csr_rw 3.000s 20.923us 20 20 100.00
spi_host_csr_aliasing 3.000s 103.918us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 23.684us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 18.987us 5 5 100.00
spi_host_csr_rw 3.000s 20.923us 20 20 100.00
spi_host_csr_aliasing 3.000s 103.918us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 23.684us 20 20 100.00
V2 TOTAL 613 690 88.84
V2S tl_intg_err spi_host_tl_intg_err 3.000s 196.521us 20 20 100.00
spi_host_sec_cm 2.000s 348.872us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 3.000s 196.521us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 47.717m 100.005ms 2 10 20.00
TOTAL 743 840 88.45

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results