SPI_HOST Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 10.700m 15.002ms 37 50 74.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 36.354us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 54.066us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 623.008us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 95.577us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 142.009us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 54.066us 20 20 100.00
spi_host_csr_aliasing 3.000s 95.577us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 14.830us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 17.526us 5 5 100.00
V1 TOTAL 102 115 88.70
V2 performance spi_host_performance 7.000s 43.505us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 1.883m 2.468ms 50 50 100.00
spi_host_error_cmd 7.000s 34.461us 50 50 100.00
spi_host_event 14.983m 21.877ms 50 50 100.00
V2 clock_rate spi_host_speed 8.017m 10.055ms 41 50 82.00
V2 speed spi_host_speed 8.017m 10.055ms 41 50 82.00
V2 chip_select_timing spi_host_speed 8.017m 10.055ms 41 50 82.00
V2 sw_reset spi_host_sw_reset 9.717m 15.001ms 37 50 74.00
V2 passthrough_mode spi_host_passthrough_mode 14.000s 183.284us 50 50 100.00
V2 cpol_cpha spi_host_speed 8.017m 10.055ms 41 50 82.00
V2 full_cycle spi_host_speed 8.017m 10.055ms 41 50 82.00
V2 duplex spi_host_smoke 10.700m 15.002ms 37 50 74.00
V2 tx_rx_only spi_host_smoke 10.700m 15.002ms 37 50 74.00
V2 stress_all spi_host_stress_all 16.983m 22.502ms 40 50 80.00
V2 spien spi_host_spien 11.667m 15.395ms 44 50 88.00
V2 stall spi_host_status_stall 7.967m 10.191ms 32 50 64.00
V2 Idlecsbactive spi_host_idlecsbactive 4.833m 10.004ms 37 50 74.00
V2 data_fifo_status spi_host_overflow_underflow 1.883m 2.468ms 50 50 100.00
V2 alert_test spi_host_alert_test 5.000s 17.898us 50 50 100.00
V2 intr_test spi_host_intr_test 11.000s 16.310us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 4.000s 230.765us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 4.000s 230.765us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 36.354us 5 5 100.00
spi_host_csr_rw 3.000s 54.066us 20 20 100.00
spi_host_csr_aliasing 3.000s 95.577us 5 5 100.00
spi_host_same_csr_outstanding 5.000s 26.103us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 36.354us 5 5 100.00
spi_host_csr_rw 3.000s 54.066us 20 20 100.00
spi_host_csr_aliasing 3.000s 95.577us 5 5 100.00
spi_host_same_csr_outstanding 5.000s 26.103us 20 20 100.00
V2 TOTAL 621 690 90.00
V2S tl_intg_err spi_host_tl_intg_err 3.000s 54.319us 20 20 100.00
spi_host_sec_cm 7.000s 78.875us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 3.000s 54.319us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 45.850m 100.005ms 2 10 20.00
TOTAL 750 840 89.29

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.92 95.70 100.00 95.07 90.46

Failure Buckets

Past Results