3e0219a2c5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 10.700m | 15.002ms | 37 | 50 | 74.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 36.354us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 54.066us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 623.008us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 95.577us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 142.009us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 54.066us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 95.577us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 14.830us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 17.526us | 5 | 5 | 100.00 |
| V1 | TOTAL | 102 | 115 | 88.70 | |||
| V2 | performance | spi_host_performance | 7.000s | 43.505us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 1.883m | 2.468ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 7.000s | 34.461us | 50 | 50 | 100.00 | ||
| spi_host_event | 14.983m | 21.877ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 8.017m | 10.055ms | 41 | 50 | 82.00 |
| V2 | speed | spi_host_speed | 8.017m | 10.055ms | 41 | 50 | 82.00 |
| V2 | chip_select_timing | spi_host_speed | 8.017m | 10.055ms | 41 | 50 | 82.00 |
| V2 | sw_reset | spi_host_sw_reset | 9.717m | 15.001ms | 37 | 50 | 74.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 14.000s | 183.284us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 8.017m | 10.055ms | 41 | 50 | 82.00 |
| V2 | full_cycle | spi_host_speed | 8.017m | 10.055ms | 41 | 50 | 82.00 |
| V2 | duplex | spi_host_smoke | 10.700m | 15.002ms | 37 | 50 | 74.00 |
| V2 | tx_rx_only | spi_host_smoke | 10.700m | 15.002ms | 37 | 50 | 74.00 |
| V2 | stress_all | spi_host_stress_all | 16.983m | 22.502ms | 40 | 50 | 80.00 |
| V2 | spien | spi_host_spien | 11.667m | 15.395ms | 44 | 50 | 88.00 |
| V2 | stall | spi_host_status_stall | 7.967m | 10.191ms | 32 | 50 | 64.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 4.833m | 10.004ms | 37 | 50 | 74.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 1.883m | 2.468ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 5.000s | 17.898us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 11.000s | 16.310us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 4.000s | 230.765us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 4.000s | 230.765us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 36.354us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 54.066us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 95.577us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 5.000s | 26.103us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 36.354us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 54.066us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 95.577us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 5.000s | 26.103us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 621 | 690 | 90.00 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 54.319us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 7.000s | 78.875us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 54.319us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 45.850m | 100.005ms | 2 | 10 | 20.00 | |
| TOTAL | 750 | 840 | 89.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.92 | 95.70 | 100.00 | 95.07 | 90.46 |
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 20 failures:
Test spi_host_upper_range_clkdiv has 5 failures.
0.spi_host_upper_range_clkdiv.50362470017089066875190051062765592716651859601340007429871676477740910776665
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100015654746 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8aa14514, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100015654746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_upper_range_clkdiv.115296823235801330519417357215753662657153064646435415166427516511185392462967
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100001890148 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd76e254, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100001890148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_smoke has 6 failures.
4.spi_host_smoke.18263129896398273117751489571637502267229775170278881091675278641371340397075
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000731290 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfb71cc94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000731290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_smoke.29423414338244062096732311229321099050452924705937320657832687998839104528683
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_smoke/latest/run.log
UVM_FATAL @ 15002845787 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x175eb654, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002845787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_spien has 2 failures.
7.spi_host_spien.112084692561176733515444540761040355112070610336017596941384720847343973956942
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_spien/latest/run.log
UVM_FATAL @ 10002558370 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9e324f14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002558370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.spi_host_spien.3666998748248755830445980050597102238716985364241683848487986029368031066768
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_spien/latest/run.log
UVM_FATAL @ 15009342054 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc62f2854, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15009342054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 4 failures.
10.spi_host_stress_all.64223936317198327420913402689978266612669171107119776842570174808066609394161
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15002964567 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5e312994, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002964567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_host_stress_all.76882208727606133871855367868404703211526177414009467865652816235335666972554
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001161403 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x21972fd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001161403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_speed has 3 failures.
14.spi_host_speed.82099677025439509663809952519877184337446132290819251267491699646708238123464
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_speed/latest/run.log
UVM_FATAL @ 10004262389 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb4981a94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004262389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.spi_host_speed.103470011755312621462083463204897912666359839142914533591991042801767821172762
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_speed/latest/run.log
UVM_FATAL @ 10001281100 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xed3f4154, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001281100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 12 failures:
Test spi_host_spien has 2 failures.
1.spi_host_spien.107788265278126282900615565554899411818620275291855674565989218454033134649358
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_spien/latest/run.log
UVM_FATAL @ 15003096816 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd1589194, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15003096816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_spien.12732135641977113160127246843662640059007326370003411212406314525698437112505
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_spien/latest/run.log
UVM_FATAL @ 10003978714 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x34e68014, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003978714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_upper_range_clkdiv has 2 failures.
2.spi_host_upper_range_clkdiv.34843129511103928609841785432466593449491652823471790698096488143913119520542
Line 317, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003600144 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x395404d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003600144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_upper_range_clkdiv.106374381108035727418082373788570801513852629186412951845082865356200341672242
Line 337, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005239077 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe2a3fa54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100005239077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 3 failures.
6.spi_host_speed.27115879694484611287985398056638598168133335191252897856573620526224084692639
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/latest/run.log
UVM_FATAL @ 10004287392 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xab290b94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004287392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_speed.97421841736916044227306016802871111795450461134344009444466751050287617039560
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_speed/latest/run.log
UVM_FATAL @ 10002255817 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x94747ed4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002255817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_smoke has 3 failures.
13.spi_host_smoke.296439870048763201322198049469348349635127526565174153968509815473963489433
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_smoke/latest/run.log
UVM_FATAL @ 15002839276 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa1e23d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002839276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_host_smoke.37776889470686386554531210872720706191038060473867076548932009020462949395583
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_smoke/latest/run.log
UVM_FATAL @ 15003134979 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfe097014, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15003134979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_stress_all has 2 failures.
13.spi_host_stress_all.54463881712361529744794229229083570125189388409369863933613611679261782010152
Line 366, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10003572399 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbc69c614, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003572399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_host_stress_all.76043395258895855773286493041851418134170512162222187231814664708747843970965
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10008114805 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe37a8154, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10008114805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 5 failures:
11.spi_host_status_stall.27046988465347677276111290004453585809467085376950938599202712183722552113813
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15008381449 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcc9814d4, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 15008381449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_status_stall.105121451046143886176908719804870294280930417464111560515334852066145727084944
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15005649846 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1ae48dd4, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 15005649846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 5 failures:
16.spi_host_idlecsbactive.53453906865086506909276943816788539477535572745569572230518493205045543697988
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004961406 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x309a3014, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10004961406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_host_idlecsbactive.12347149414296548215792672322731743468139083871725684412108077447503023622367
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15004010692 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9ae79814, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15004010692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 4 failures:
1.spi_host_status_stall.18195162249823838931627724893670184489388530264712577787180292910352646517947
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_ERROR @ 3976546 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 3976546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_host_status_stall.21247725390178515170397491664877445320754724574456699882067291410642913627364
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log
UVM_ERROR @ 4123709 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 4123709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 4 failures:
10.spi_host_idlecsbactive.402179672063275723704262330219766960985882434334288191960804912236977114353
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10003652337 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1c2e7914, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10003652337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_idlecsbactive.8464931750238414805381643266731120854699931006574677632595144273731524900576
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10008403151 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4c857254, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10008403151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 3 failures:
2.spi_host_idlecsbactive.3685627666809881251104139106262099947187730932574322724895731866924080461828
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10018043835 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4b992214, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10018043835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_idlecsbactive.45091721417859591777229800132816611015841971979806742587000742046236003537283
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10009584879 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x342bf14, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10009584879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 3 failures:
43.spi_host_sw_reset.58155803864973305703082060713186311584237259947107131845622981767112029056171
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001548665 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc56cb554, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10001548665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.spi_host_sw_reset.24553604943971757071494910753199113275093851455807754295295326158816405792151
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15005083686 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7e5da454, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 15005083686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:
0.spi_host_status_stall.1376414457557494211336586629347580082463901343789817499252104692748972298685
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_status_stall/latest/run.log
UVM_ERROR @ 12213170 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 12213170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.spi_host_status_stall.46741596255663751658086309270657668983942457176659854507640471859089648081797
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_status_stall/latest/run.log
UVM_ERROR @ 5275741 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5275741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 2 failures:
Test spi_host_speed has 1 failures.
2.spi_host_speed.17146675192755173154868087850467615344564410085311563116890246598957615434642
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_speed/latest/run.log
UVM_FATAL @ 10054297076 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xefec7ed4, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10054297076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
42.spi_host_spien.85908582959456863039169916565057548436471847198389791896387366161920677134367
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_spien/latest/run.log
UVM_FATAL @ 15395105701 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x92d90214, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 15395105701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 2 failures:
9.spi_host_sw_reset.94887495378885383636797952294125587875885421462860673119451530684187407285204
Line 387, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10022864554 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3ea28f54, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
UVM_INFO @ 10022864554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_host_sw_reset.34069893398129272526450066620145192517073292194426095228945953544730151960743
Line 393, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10007429378 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1ee04614, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
UVM_INFO @ 10007429378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 2 failures:
12.spi_host_smoke.37461095820934039086676222211548369542971980087645416168083455081942908605690
Line 397, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_smoke/latest/run.log
UVM_FATAL @ 16871713164 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc6682994, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
UVM_INFO @ 16871713164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.spi_host_smoke.89643034014244636747097388825560585419720298928687222913034366210934570322684
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_smoke/latest/run.log
UVM_FATAL @ 16697930464 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7089b694, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
UVM_INFO @ 16697930464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
1.spi_host_upper_range_clkdiv.110695674397920715955171037200195537985441903975351157373963406274090213613194
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:c3fb66d8-51f5-47d2-b697-38e7919ba711
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=36) has 1 failures:
5.spi_host_speed.23729953836407992852121991473442994315289247833789080132588154631895734982332
Line 437, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_speed/latest/run.log
UVM_FATAL @ 10055390499 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb4466f54, Comparison=CompareOpEq, exp_data=0x1, call_count=36)
UVM_INFO @ 10055390499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
5.spi_host_sw_reset.28233374009954026810140392732944808459861607157058833702628268655640396931683
Line 308, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10004030805 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2f43154, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10004030805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=81) has 1 failures:
5.spi_host_status_stall.56628741789964382664800208850008630028097607209605618716607408845707869389623
Line 929, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10191149057 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb99c1dd4, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
UVM_INFO @ 10191149057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
6.spi_host_sw_reset.94165796787171413170308756040123894135819539684760965810801713334602088665409
Line 360, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10033295492 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x56af0854, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10033295492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=76) has 1 failures:
7.spi_host_status_stall.16928556801843701930631814978159991328485837703230534729580143074905334561321
Line 895, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
UVM_FATAL @ 17577413560 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb7877a94, Comparison=CompareOpEq, exp_data=0x1, call_count=76)
UVM_INFO @ 17577413560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
9.spi_host_status_stall.11644745396399231466668938069671800027571888068409857289023305018036980891275
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003333021 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xbc169814, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10003333021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
10.spi_host_smoke.109281665784604765948975424280012442404160932018275140181122179172467342754798
Line 385, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
UVM_FATAL @ 23129843844 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcd2aed14, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 23129843844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
13.spi_host_status_stall.3168201855533794283607908219375330655547919609064019122997168735622269316901
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10023679328 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf41e8a14, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10023679328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
15.spi_host_sw_reset.37417692536672467098838944616506883137812126096991951064559637694472246246918
Line 336, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15005090670 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x95d166d4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15005090670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=35) has 1 failures:
16.spi_host_sw_reset.13088724085817425197928320737969640309966326998949982892394158732550096675331
Line 466, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10101263801 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc6001914, Comparison=CompareOpEq, exp_data=0x0, call_count=35)
UVM_INFO @ 10101263801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=40) has 1 failures:
19.spi_host_smoke.62214049950296391398802834820093223558777916137606191551884735001317036488745
Line 443, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_smoke/latest/run.log
UVM_FATAL @ 10077233952 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xba871e54, Comparison=CompareOpEq, exp_data=0x1, call_count=40)
UVM_INFO @ 10077233952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
23.spi_host_stress_all.103687719677647235458981274605056993644274866599886115365372419405874530891270
Line 331, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15025080903 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9382f7d4, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 15025080903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=34) has 1 failures:
24.spi_host_stress_all.66560564162944237134454687219390642585617999628169191924596302639243606761028
Line 472, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10230011445 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd7534654, Comparison=CompareOpEq, exp_data=0x0, call_count=34)
UVM_INFO @ 10230011445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
26.spi_host_sw_reset.24859357273132784912722787345080985778359323829048883510140454120794881248308
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10006709272 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfb42d214, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10006709272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
28.spi_host_sw_reset.83033601151348930132288206696352305457530254364883130688884972282938062603857
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001594325 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x59e61614, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10001594325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
28.spi_host_spien.112106309612316358792894906094698136841697862705006104804484401786302293229523
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_spien/latest/run.log
UVM_FATAL @ 10179302465 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x449b06d4, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
UVM_INFO @ 10179302465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
37.spi_host_sw_reset.71354385268741605723044256138140582085904481134025004464265802683247794468794
Line 330, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10015877377 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb6bcba14, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10015877377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
38.spi_host_sw_reset.67235824834007071267504085140895541827254174459343424337799095213682925129194
Line 352, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15001429453 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa3123514, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 15001429453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
39.spi_host_status_stall.33303763268810393130409944971592194613895461604496123924059836693153935997799
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10001784143 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1c911dd4, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10001784143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=84) has 1 failures:
41.spi_host_status_stall.98234144845850529498308651493912560781237267008687592355435787642660648601298
Line 937, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
UVM_FATAL @ 17685292820 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5b7db594, Comparison=CompareOpEq, exp_data=0x1, call_count=84)
UVM_INFO @ 17685292820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=78) has 1 failures:
42.spi_host_status_stall.38209294926251875170834661147938036237919599343636572910667273918330253034352
Line 885, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_status_stall/latest/run.log
UVM_FATAL @ 16328456344 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9875ca54, Comparison=CompareOpEq, exp_data=0x1, call_count=78)
UVM_INFO @ 16328456344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
43.spi_host_speed.71699657637802352288946607697508219023269471574036363944951582721212482638684
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_speed/latest/run.log
UVM_FATAL @ 10014791927 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7cca8e94, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10014791927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=32) has 1 failures:
44.spi_host_stress_all.42661575289975605600311503452690318219563803030913604215190767961913706935009
Line 471, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10022877361 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe261d6d4, Comparison=CompareOpEq, exp_data=0x0, call_count=32)
UVM_INFO @ 10022877361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
45.spi_host_idlecsbactive.16092246159838744204575661760888249427797300108952609499382380538787743748081
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=38) has 1 failures:
48.spi_host_stress_all.99971368397083303190379012674488382942799221636511830383728466469591453964910
Line 483, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22590874832 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc31cb9d4, Comparison=CompareOpEq, exp_data=0x0, call_count=38)
UVM_INFO @ 22590874832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---