0bfa990ddc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 17.417m | 15.001ms | 37 | 50 | 74.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 7.000s | 110.104us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 12.000s | 17.748us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 4.000s | 610.336us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 7.000s | 16.864us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 10.000s | 42.375us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 12.000s | 17.748us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 7.000s | 16.864us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 152.037us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 33.331us | 5 | 5 | 100.00 |
| V1 | TOTAL | 102 | 115 | 88.70 | |||
| V2 | performance | spi_host_performance | 3.000s | 35.704us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 1.250m | 18.160ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 3.000s | 44.325us | 50 | 50 | 100.00 | ||
| spi_host_event | 14.083m | 21.446ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 12.533m | 10.001ms | 34 | 50 | 68.00 |
| V2 | speed | spi_host_speed | 12.533m | 10.001ms | 34 | 50 | 68.00 |
| V2 | chip_select_timing | spi_host_speed | 12.533m | 10.001ms | 34 | 50 | 68.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.100m | 15.003ms | 41 | 50 | 82.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 314.923us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 12.533m | 10.001ms | 34 | 50 | 68.00 |
| V2 | full_cycle | spi_host_speed | 12.533m | 10.001ms | 34 | 50 | 68.00 |
| V2 | duplex | spi_host_smoke | 17.417m | 15.001ms | 37 | 50 | 74.00 |
| V2 | tx_rx_only | spi_host_smoke | 17.417m | 15.001ms | 37 | 50 | 74.00 |
| V2 | stress_all | spi_host_stress_all | 17.950m | 15.013ms | 36 | 50 | 72.00 |
| V2 | spien | spi_host_spien | 7.267m | 10.002ms | 40 | 50 | 80.00 |
| V2 | stall | spi_host_status_stall | 8.267m | 11.724ms | 35 | 50 | 70.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 14.517m | 200.000ms | 41 | 50 | 82.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 1.250m | 18.160ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 20.972us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 12.000s | 29.964us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 9.000s | 40.613us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 9.000s | 40.613us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 7.000s | 110.104us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 12.000s | 17.748us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 7.000s | 16.864us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 10.000s | 53.961us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 7.000s | 110.104us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 12.000s | 17.748us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 7.000s | 16.864us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 10.000s | 53.961us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 617 | 690 | 89.42 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 13.000s | 90.544us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 259.542us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 13.000s | 90.544us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 48.083m | 173.755ms | 0 | 10 | 0.00 | |
| TOTAL | 744 | 840 | 88.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 90.99 | 90.92 | 83.18 | 92.77 | 89.61 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 27 failures:
0.spi_host_speed.4535612807296464482845617808454503355497588617088576176112504111283273684649
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log
UVM_FATAL @ 10002084296 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc4da9954, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002084296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_speed.67908785005165011290271707385860284724374630539009213338154367878082558776048
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_speed/latest/run.log
UVM_FATAL @ 10000839478 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb1f49514, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000839478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
0.spi_host_upper_range_clkdiv.64701003139003039561200548480675065408156477491467560118346761123973637599073
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100015173527 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x99c84314, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100015173527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_upper_range_clkdiv.95087714324188493636851811056038536239237831257391684844052472777679951516035
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002713263 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x52519414, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100002713263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
4.spi_host_smoke.31032860733444278173203226970332613944999100060197923627294511070727166398149
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
UVM_FATAL @ 15003147468 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5c9d2654, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15003147468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_smoke.12995679408564012206092102175155482387228321554707477318636894243195067547292
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000681165 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd2885514, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000681165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
16.spi_host_stress_all.24423328447370080234898788729822473784411962436336564473077220613642570981295
Line 348, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15004887184 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd3aff54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15004887184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_stress_all.11318031534461109337965634846829327246497451165776682187706106996379173668216
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15004425904 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xecc24654, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15004425904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
18.spi_host_spien.107308400375954581316692001146142139311991136985132558861404876031474786218030
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_spien/latest/run.log
UVM_FATAL @ 10003255596 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf2f80dd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003255596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_host_spien.52617788132425659987524858261853889468408709605702851161498840637010468799022
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_spien/latest/run.log
UVM_FATAL @ 10004524929 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdc94e154, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004524929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 12 failures:
Test spi_host_stress_all has 3 failures.
0.spi_host_stress_all.2988885379241222615298127867707150347574562172106871798944241859534563187515
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10002097836 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe2518394, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002097836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_stress_all.77604444100928773820662742932462587419708756534057255445231609978393698266814
Line 374, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15002160120 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbe41f214, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002160120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_speed has 4 failures.
1.spi_host_speed.103200362713646186694710602943839154397405455735713297186701032863029401397401
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_speed/latest/run.log
UVM_FATAL @ 10000955063 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9ba579d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000955063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_speed.102367598558073342673184206036694174916306589390209185861616826154421874974194
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_speed/latest/run.log
UVM_FATAL @ 10000992610 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2781c654, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000992610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_spien has 2 failures.
8.spi_host_spien.79620445735710939600362840688857895583699413277801084913725439204154022175093
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_spien/latest/run.log
UVM_FATAL @ 10001285737 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x38f82614, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001285737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.spi_host_spien.15307836778579622849587964415448823055685940656936633377885626600649378469586
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_spien/latest/run.log
UVM_FATAL @ 10009726092 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x20076454, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10009726092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 3 failures.
12.spi_host_smoke.84466737525594018771373703157191511112747193951644861945466361117905586256411
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000644615 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb3c2a554, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000644615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_host_smoke.52258103815735928965572979050356154102677729002948686385280287281450827458488
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000820095 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7b65d3d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000820095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
3.spi_host_upper_range_clkdiv.56253479568951320870330201988003823795640232566218566687517520473977584542233
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:10af8efc-9d0c-4a17-bb7a-9b066134defc
4.spi_host_upper_range_clkdiv.48266577606681199755106664024393591324188315990882761250059085782491255595334
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:fbf766f9-d0be-486c-9857-e9613232b718
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
10.spi_host_idlecsbactive.62165573236172613977247536648597061391392649448963105817932915235644485471259
Line 387, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_host_idlecsbactive.50972353728769499250188901210164946942586960657732416145701727334419756402308
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 3 failures:
Test spi_host_idlecsbactive has 2 failures.
4.spi_host_idlecsbactive.96032179452854788172009331640651259488247804564002440475135589170831717224548
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002453335 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xaac5ea54, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10002453335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.spi_host_idlecsbactive.17954807146680918957448282431880896150915785891100553245366603410242069222978
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15024286341 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4f2be1d4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 15024286341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_upper_range_clkdiv has 1 failures.
7.spi_host_upper_range_clkdiv.46153694641751027794941987189139129615716306872785884333619054698764390307689
Line 329, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003168351 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1168c94, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 100003168351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 3 failures:
21.spi_host_status_stall.77205563717211763933632757066514948155924190287834401411311645282877473131707
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10002795133 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4fa528d4, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10002795133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.spi_host_status_stall.76528604458551199017594589669139008110267246081310839087210029789728123609435
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10015629401 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa5229194, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10015629401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 3 failures:
24.spi_host_idlecsbactive.34198421229584006642571676890109490967948793295660960850945105949918264628755
Line 331, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10009582365 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x42d24094, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10009582365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_host_idlecsbactive.17964270403274233673865067258406178104194977493175749934919604445199413244691
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15008134552 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x115563d4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15008134552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 2 failures:
Test spi_host_status_stall has 1 failures.
3.spi_host_status_stall.4743766753276443112615244097617601971036807302082475569086933244117432563350
Line 411, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10036204096 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x819aad4, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10036204096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
6.spi_host_speed.10830296610131554293819443043479723835150405604003102878662285149181257035893
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/latest/run.log
UVM_FATAL @ 10148015419 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6a907494, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10148015419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
7.spi_host_sw_reset.10605448469279508330833183613204183099855689983944064198782591101033181322282
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15070462870 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3f061754, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 15070462870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.spi_host_sw_reset.98324745349648322112396126835004048281370173742082039865209366526435150682677
Line 366, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10007561976 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf7b01454, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10007561976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:
7.spi_host_status_stall.76349707300720901698389769255413735639686097774768902796566244809008269488483
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
UVM_ERROR @ 3530020 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3530020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_status_stall.25592774513801174225121618250016285089732887291153049463054331449478487642330
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log
UVM_ERROR @ 3351226 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3351226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 2 failures:
8.spi_host_sw_reset.88840542459460342945345462040782683527744943324405278855659946263107111187588
Line 308, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15003160491 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcea20794, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 15003160491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_sw_reset.48678594288450362005414373275681339058266355076671524606774551414498622574645
Line 312, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15006941660 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe4d15b54, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 15006941660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 2 failures:
Test spi_host_status_stall has 1 failures.
11.spi_host_status_stall.107458978384316361239900862901651190749921427184915741105414509509257900564192
Line 393, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10022084434 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7be99754, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10022084434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
35.spi_host_speed.14726990603984907723593150568583631635819405807036208286848968569487647400517
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_speed/latest/run.log
UVM_FATAL @ 10031270495 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2e4e9454, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10031270495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 2 failures:
Test spi_host_spien has 1 failures.
29.spi_host_spien.33309136637855497782270889712041032869037787624369767828144390641163587505918
Line 379, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_spien/latest/run.log
UVM_FATAL @ 10026068478 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2ea2ef94, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10026068478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
41.spi_host_stress_all.65614837005796225882248239835713738078348704994963290065230507541467581419549
Line 405, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15156210548 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xaea53654, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 15156210548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
1.spi_host_status_stall.36689608482913172836072280311937266007826598973000828734111106863347695058544
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10004168081 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x625517d4, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10004168081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
1.spi_host_spien.98986342452453843528591988755970700396851172020311045524353816500406669617911
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_spien/latest/run.log
UVM_FATAL @ 16376307051 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xef8078d4, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 16376307051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
2.spi_host_upper_range_clkdiv.77626571838642998735568947219015030178798266236927794561032411328091200542501
Line 379, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 173755330507 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3b1ecf54, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
UVM_INFO @ 173755330507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=76) has 1 failures:
3.spi_host_speed.84624106980561605639371192698470148714069936283822291463284888576788415247218
Line 687, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_speed/latest/run.log
UVM_FATAL @ 10156728703 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xfac3fd14, Comparison=CompareOpEq, exp_data=0x0, call_count=76)
UVM_INFO @ 10156728703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
8.spi_host_upper_range_clkdiv.32645640487876524734990965271916536694595472266002934769360506845742370433970
Line 379, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 168945782616 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9a5f6dd4, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 168945782616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
10.spi_host_sw_reset.38919091753297712106713011725872798899737496235568013376942959589825723872942
Line 379, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15515028212 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfa795e54, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
UVM_INFO @ 15515028212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
13.spi_host_status_stall.112396395343815274463836013636721691830118097996203011602504075365444851923522
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10014863716 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x64dd6594, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10014863716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
13.spi_host_stress_all.2103901821091023633901384230214252944306813635738913892337804622326315019648
Line 410, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15013321651 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbf006314, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 15013321651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
14.spi_host_sw_reset.30648773523132465262787693324418135002276195659595612446216671003777524177641
Line 348, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002771992 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x73d147d4, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10002771992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 1 failures:
15.spi_host_status_stall.113588018833494291263034200849899425168172368854113194554881660585871101271445
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log
UVM_ERROR @ 2596602 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 2596602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=34) has 1 failures:
15.spi_host_spien.80317886866599536582951168414366818495615183280865250303262708091550205734845
Line 509, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_spien/latest/run.log
UVM_FATAL @ 10091696156 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2ad09254, Comparison=CompareOpEq, exp_data=0x1, call_count=34)
UVM_INFO @ 10091696156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=45) has 1 failures:
18.spi_host_stress_all.37189371561514974891419905468117221404148083218253360417686872771992364300268
Line 494, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15163738857 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xac7b5394, Comparison=CompareOpEq, exp_data=0x0, call_count=45)
UVM_INFO @ 15163738857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
19.spi_host_smoke.59559918258369258060511517587599057210361529492437008279548255521964758743736
Line 947, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_smoke/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=32) has 1 failures:
22.spi_host_stress_all.72209533939630599446491067826945491465791928071682574467235691858445386050076
Line 486, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15229570313 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd699c354, Comparison=CompareOpEq, exp_data=0x0, call_count=32)
UVM_INFO @ 15229570313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
25.spi_host_stress_all.93382406378807146767001055917029923687108202643844052925785737279233042205695
Line 426, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15098085243 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xca0420d4, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 15098085243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
26.spi_host_spien.60680789448188219985698729371897065630061107481940845358165250036548359772954
Line 397, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_spien/latest/run.log
UVM_FATAL @ 10111058739 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7fdf0314, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
UVM_INFO @ 10111058739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
29.spi_host_status_stall.66610163543178416696960728335782063577014283030608004895086733703294192186143
Line 395, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10074544203 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xdafae654, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10074544203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
30.spi_host_sw_reset.15488919404462075788554248112810796831392182998628883252959467474324144525017
Line 436, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10125754037 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x25371a94, Comparison=CompareOpEq, exp_data=0x0, call_count=30)
UVM_INFO @ 10125754037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
33.spi_host_status_stall.82414324483358897999267047788784758669773907597417009941452484387446722969731
Line 459, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10009661732 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8fc5c994, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
UVM_INFO @ 10009661732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
36.spi_host_spien.72832023556118997339087021616330591880558950708833575974456862070284774398414
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_spien/latest/run.log
UVM_FATAL @ 16414949815 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x826b9e54, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 16414949815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
37.spi_host_sw_reset.9626482355422527854531768346092421527152246065240205268629853542530848270426
Line 405, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10024655822 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa0389d94, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
UVM_INFO @ 10024655822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
40.spi_host_status_stall.74535215025449906571546652680123936515301310266811955699055350113027168652527
Line 417, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10128307850 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x54fc99d4, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10128307850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=38) has 1 failures:
41.spi_host_speed.55548938190614934095456865789894711062571805399592025332300494953029407897803
Line 441, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_speed/latest/run.log
UVM_FATAL @ 10466254060 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2061d594, Comparison=CompareOpEq, exp_data=0x1, call_count=38)
UVM_INFO @ 10466254060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
42.spi_host_status_stall.112810561242568933702042615533577855808005814172319824268386662490121079387612
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10007141630 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc97af354, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10007141630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
44.spi_host_sw_reset.14150175739103065160776258401184986030097461972510292186860963355285653637310
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10015586684 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7daca7d4, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10015586684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
45.spi_host_smoke.109068146512818852151155116413956086742478081397483952627744623542322818840813
Line 371, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_smoke/latest/run.log
UVM_FATAL @ 15030156138 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb3681a54, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 15030156138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
46.spi_host_stress_all.39859752558799605985466917671476810694107999013167957714394076418725398364506
Line 445, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15368850028 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb49b7494, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
UVM_INFO @ 15368850028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=79) has 1 failures:
48.spi_host_status_stall.109040179308379194485362994946916499645764100855004199838561292284310130447038
Line 925, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10565936253 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5e0e2654, Comparison=CompareOpEq, exp_data=0x1, call_count=79)
UVM_INFO @ 10565936253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---