SPI_HOST Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 11.817m 15.470ms 34 50 68.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 19.576us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 46.387us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 254.486us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 38.742us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 27.935us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 46.387us 20 20 100.00
spi_host_csr_aliasing 3.000s 38.742us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 29.748us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 16.970us 5 5 100.00
V1 TOTAL 99 115 86.09
V2 performance spi_host_performance 13.000s 117.301us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 1.483m 1.884ms 50 50 100.00
spi_host_error_cmd 7.000s 24.566us 50 50 100.00
spi_host_event 13.867m 74.997ms 50 50 100.00
V2 clock_rate spi_host_speed 5.350m 10.001ms 38 50 76.00
V2 speed spi_host_speed 5.350m 10.001ms 38 50 76.00
V2 chip_select_timing spi_host_speed 5.350m 10.001ms 38 50 76.00
V2 sw_reset spi_host_sw_reset 10.250m 15.146ms 42 50 84.00
V2 passthrough_mode spi_host_passthrough_mode 13.000s 787.566us 50 50 100.00
V2 cpol_cpha spi_host_speed 5.350m 10.001ms 38 50 76.00
V2 full_cycle spi_host_speed 5.350m 10.001ms 38 50 76.00
V2 duplex spi_host_smoke 11.817m 15.470ms 34 50 68.00
V2 tx_rx_only spi_host_smoke 11.817m 15.470ms 34 50 68.00
V2 stress_all spi_host_stress_all 17.483m 15.002ms 44 50 88.00
V2 spien spi_host_spien 6.217m 10.001ms 41 50 82.00
V2 stall spi_host_status_stall 7.650m 10.001ms 32 50 64.00
V2 Idlecsbactive spi_host_idlecsbactive 12.650m 200.000ms 37 50 74.00
V2 data_fifo_status spi_host_overflow_underflow 1.483m 1.884ms 50 50 100.00
V2 alert_test spi_host_alert_test 22.000s 16.852us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 16.787us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 350.240us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 350.240us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 19.576us 5 5 100.00
spi_host_csr_rw 3.000s 46.387us 20 20 100.00
spi_host_csr_aliasing 3.000s 38.742us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 20.677us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 19.576us 5 5 100.00
spi_host_csr_rw 3.000s 46.387us 20 20 100.00
spi_host_csr_aliasing 3.000s 38.742us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 20.677us 20 20 100.00
V2 TOTAL 624 690 90.43
V2S tl_intg_err spi_host_tl_intg_err 3.000s 681.903us 20 20 100.00
spi_host_sec_cm 8.000s 77.816us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 3.000s 681.903us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 53.383m 174.615ms 1 10 10.00
TOTAL 749 840 89.17

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results