e439226b6c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 11.817m | 15.470ms | 34 | 50 | 68.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 19.576us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 46.387us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 254.486us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 38.742us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 27.935us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 46.387us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 38.742us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 29.748us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 2.000s | 16.970us | 5 | 5 | 100.00 |
| V1 | TOTAL | 99 | 115 | 86.09 | |||
| V2 | performance | spi_host_performance | 13.000s | 117.301us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 1.483m | 1.884ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 7.000s | 24.566us | 50 | 50 | 100.00 | ||
| spi_host_event | 13.867m | 74.997ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 5.350m | 10.001ms | 38 | 50 | 76.00 |
| V2 | speed | spi_host_speed | 5.350m | 10.001ms | 38 | 50 | 76.00 |
| V2 | chip_select_timing | spi_host_speed | 5.350m | 10.001ms | 38 | 50 | 76.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.250m | 15.146ms | 42 | 50 | 84.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 13.000s | 787.566us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 5.350m | 10.001ms | 38 | 50 | 76.00 |
| V2 | full_cycle | spi_host_speed | 5.350m | 10.001ms | 38 | 50 | 76.00 |
| V2 | duplex | spi_host_smoke | 11.817m | 15.470ms | 34 | 50 | 68.00 |
| V2 | tx_rx_only | spi_host_smoke | 11.817m | 15.470ms | 34 | 50 | 68.00 |
| V2 | stress_all | spi_host_stress_all | 17.483m | 15.002ms | 44 | 50 | 88.00 |
| V2 | spien | spi_host_spien | 6.217m | 10.001ms | 41 | 50 | 82.00 |
| V2 | stall | spi_host_status_stall | 7.650m | 10.001ms | 32 | 50 | 64.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 12.650m | 200.000ms | 37 | 50 | 74.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 1.483m | 1.884ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 22.000s | 16.852us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 16.787us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 350.240us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 350.240us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 19.576us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 46.387us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 38.742us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 20.677us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 19.576us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 46.387us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 38.742us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 20.677us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 624 | 690 | 90.43 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 681.903us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 8.000s | 77.816us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 681.903us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 53.383m | 174.615ms | 1 | 10 | 10.00 | |
| TOTAL | 749 | 840 | 89.17 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.84 | 95.70 | 100.00 | 95.07 | 90.87 |
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 16 failures:
Test spi_host_upper_range_clkdiv has 3 failures.
0.spi_host_upper_range_clkdiv.65295383670586552790646381376307980572139486529970482763569267248931464514960
Line 331, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100001414841 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbda3e094, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100001414841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_upper_range_clkdiv.81795675988170149910424088832092059098616249474535274369838710025833602832865
Line 303, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100021530863 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf47ad1d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100021530863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_speed has 6 failures.
6.spi_host_speed.97753759212892239021766935766401602254578541448498995468329528320367986651440
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/latest/run.log
UVM_FATAL @ 10004078909 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xaa439654, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004078909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_speed.94976024836588262200574156222846634244169950565562503865676538417381268875178
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_speed/latest/run.log
UVM_FATAL @ 10000752113 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x32042394, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000752113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_smoke has 3 failures.
10.spi_host_smoke.42842882082675281120333943882112661341076289568352999224113510837844857150992
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
UVM_FATAL @ 15004124857 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x859c8fd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15004124857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_host_smoke.54699425829137741186626073983103736535414595358715785384556560786276948191188
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_smoke/latest/run.log
UVM_FATAL @ 15004126854 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xeae69f54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15004126854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_stress_all has 2 failures.
24.spi_host_stress_all.101190556685839943289717294085077388965535931598968706289638516385524714636328
Line 333, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001893333 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x463ae294, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001893333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_host_stress_all.3012111384852090338331174352877643580708249643239165092755106636097600342151
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001645964 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1a676954, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001645964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 2 failures.
46.spi_host_spien.112906262041174602519619542069058271891694841531477618139999907386629176488246
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_spien/latest/run.log
UVM_FATAL @ 10002682169 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8f7dac54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002682169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.spi_host_spien.88048162771281918450677816801206530146508927620538001181842059749968514987378
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_spien/latest/run.log
UVM_FATAL @ 10003517953 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xba4c75d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003517953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 16 failures:
Test spi_host_smoke has 7 failures.
3.spi_host_smoke.3590945758549125883743283634327955327373506375903083923601828515509259334798
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001628900 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x70768994, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001628900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_smoke.79094426222007243473563102901947913639547618050209313684845047637153690068426
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
UVM_FATAL @ 15003956607 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x98f75f94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15003956607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_host_upper_range_clkdiv has 3 failures.
5.spi_host_upper_range_clkdiv.87755839260116677733652170097209220727570855926502357395573184619131971098723
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003730147 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd5cb7ed4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003730147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_upper_range_clkdiv.102751270004863209214115487509484342388388704520935958953931938468536766921409
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100007583332 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2fdf5914, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100007583332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_spien has 4 failures.
5.spi_host_spien.41979772716088878531498071013785155489426067443959323384691200551935043201729
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_spien/latest/run.log
UVM_FATAL @ 10001019096 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x873a7254, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001019096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_host_spien.75426475916728391162095287755422554842417771215577991720129155696998005574605
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_spien/latest/run.log
UVM_FATAL @ 10001291763 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x12ee394, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001291763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_speed has 1 failures.
20.spi_host_speed.13899561656737553754423691847457487977228814256820391321988644724101103750047
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_speed/latest/run.log
UVM_FATAL @ 10010731753 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6b1dc254, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10010731753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
43.spi_host_stress_all.58596882711278113272954012190983423535522679421165460860028446443908254712652
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10008993739 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x48e8cb14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10008993739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 5 failures:
0.spi_host_idlecsbactive.75343225656581024414004887388768062227549329611551299348869616907708672187358
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004102205 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf5719d94, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10004102205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_idlecsbactive.99058499591118666583779046512163003163913347299458369693385998800384980057789
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004434278 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9fb40494, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10004434278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 5 failures:
3.spi_host_status_stall.32891263220426839340228894525861229840230727079205275732271878074591946014708
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log
UVM_ERROR @ 6601118 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6601118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_status_stall.97371176934700980595890365009506284389191887105350813923306017191832741741215
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
UVM_ERROR @ 3224188 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3224188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 3 failures:
9.spi_host_status_stall.98488066186463490003036426713248035652371540919220569539177288488025829173801
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10002824101 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf67d6d4, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10002824101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.spi_host_status_stall.10152136887383226243694520104605518848171062751820123342122851464250878204609
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15028780258 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x198c7954, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 15028780258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 3 failures:
10.spi_host_idlecsbactive.63733244351864834103072591114576116176407010370326574965216531923160119139418
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10017367623 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x47953614, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10017367623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.spi_host_idlecsbactive.40379904279716076652218275292668203563594949643100643889321167817791475257974
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10014374966 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa662c54, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10014374966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 3 failures:
Test spi_host_spien has 1 failures.
12.spi_host_spien.104108226931492809684961061901394468893699245024936998755761954084249446436642
Line 393, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_spien/latest/run.log
UVM_FATAL @ 10008124771 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3c5f08d4, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10008124771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
18.spi_host_speed.24451898280261198064889785853579116200893989150275989999277131724204958834497
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_speed/latest/run.log
UVM_FATAL @ 10330403416 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x27a0d9d4, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10330403416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
23.spi_host_smoke.25608782897855922825046250980612573445987533504914687890728799932615256399892
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_smoke/latest/run.log
UVM_FATAL @ 15470464812 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6f623654, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 15470464812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 2 failures:
Test spi_host_smoke has 1 failures.
0.spi_host_smoke.94982352603711887031927594725004187691425928261523426426524579098760114120114
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
UVM_FATAL @ 15269733800 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8089dd4, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 15269733800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
28.spi_host_speed.82720860488191517337522435163727946207796001455563236900381523380006934534348
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_speed/latest/run.log
UVM_FATAL @ 10019128120 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x595a4514, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10019128120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 2 failures:
Test spi_host_upper_range_clkdiv has 1 failures.
1.spi_host_upper_range_clkdiv.42357782661612574157520989337303014443703132083342464008977361705134578152604
Line 387, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 174614931015 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x15e3de94, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 174614931015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 1 failures.
36.spi_host_smoke.70115074020048603631017200204512335548202028098681465312887367099200296979928
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_smoke/latest/run.log
UVM_FATAL @ 16251460144 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xbb8abfd4, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 16251460144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
2.spi_host_sw_reset.34476948116171811750862457955965052193595448443655011091238060071767858819798
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10016758896 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x570cbb54, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10016758896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_sw_reset.59468747958238679139694423494624337467797444429849804675573521555353573636025
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003621510 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x96e83a54, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10003621510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
2.spi_host_idlecsbactive.7899076569143306767835624219243948289560790665488331232413830583609897007929
Line 395, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.spi_host_idlecsbactive.64589905593225512235164946252239074539504674521974685314062402361725028545297
Line 411, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
3.spi_host_upper_range_clkdiv.31757866501901967433593905369532885021029079448836859859828291472772153088004
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:ba09c703-6c65-4297-a5eb-0face586e3bd
9.spi_host_upper_range_clkdiv.96215269621800750358558596559692605223480902011782042146897700686942419258610
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:06999987-de20-4e27-895f-947c5f9ea981
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
5.spi_host_status_stall.51726267904576768949537170973940261767597355575080100205014934871416827813410
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003615967 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x65b02014, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10003615967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.spi_host_status_stall.19748039473601044513935231635467549655881806902496559157883507686654707414056
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10001433616 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd57c4654, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10001433616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 2 failures:
Test spi_host_smoke has 1 failures.
13.spi_host_smoke.37625139034072126733161906206806023408511829067823600730479666404492593091901
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_smoke/latest/run.log
UVM_FATAL @ 15926042686 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcb2cac14, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 15926042686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
34.spi_host_spien.27918232126329001752973922724893734092735867707723206698243201427962131508284
Line 395, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_spien/latest/run.log
UVM_FATAL @ 10028998697 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb1661c94, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 10028998697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 2 failures:
15.spi_host_status_stall.28286049519799756364460998570720490675691812940254769480224670767032404366966
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log
UVM_ERROR @ 9191839 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 9191839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_status_stall.53196172947927434184987414241916898223892586913023943293520832824935080941276
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log
UVM_ERROR @ 4428041 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 4428041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
23.spi_host_idlecsbactive.64912750006018749105570176050007024334802167125332241251910031186638581957944
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004730258 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc0e8c0d4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10004730258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_host_idlecsbactive.97555001144956687395355466570855494008686347828467788019221096243695180587982
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10005395657 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3bc6ba94, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10005395657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 2 failures:
26.spi_host_speed.98778250640779710373032158815831325737469286789345087206498287172112710135078
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_speed/latest/run.log
UVM_FATAL @ 10018369179 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6c003d14, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10018369179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.spi_host_speed.93532159564695873981788477305752217624357195034771755523140243368007708442768
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_speed/latest/run.log
UVM_FATAL @ 10013148006 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x483b2254, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10013148006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=81) has 1 failures:
1.spi_host_status_stall.61111780243018632259932343944011988533502638909521972402775675209336985836725
Line 909, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 11630643126 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x126ec254, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
UVM_INFO @ 11630643126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=32) has 1 failures:
2.spi_host_stress_all.46633542548936614251536360040090156464333015203855134427018492055709993108944
Line 479, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15092716143 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x80352514, Comparison=CompareOpEq, exp_data=0x0, call_count=32)
UVM_INFO @ 15092716143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
5.spi_host_speed.104125304600512750723222783116758803114863108882435209806181087003801509211400
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_speed/latest/run.log
UVM_FATAL @ 10052416581 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xaeb6f5d4, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10052416581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
6.spi_host_status_stall.23028303322430742712632085423191911321421815203675442952578677263767447414821
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10027515645 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfd0d30d4, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10027515645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
8.spi_host_sw_reset.42151801633188351912293692642304847250189342171783516912500754113747326669088
Line 352, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10012859063 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x870659d4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10012859063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=88) has 1 failures:
11.spi_host_status_stall.66983656236599423901546260103735647535316728261213314809078773914618347786864
Line 941, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_FATAL @ 22578534191 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2d7ff094, Comparison=CompareOpEq, exp_data=0x1, call_count=88)
UVM_INFO @ 22578534191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
13.spi_host_status_stall.79505499500396088505874034002963761383487208992934193027688734370085437378347
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10006047070 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8e4d9554, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10006047070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
17.spi_host_smoke.89766749637889656801810847317628867743214030863299707683998693357882743050091
Line 379, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_smoke/latest/run.log
UVM_FATAL @ 16679162999 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfff1f614, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 16679162999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
18.spi_host_sw_reset.89466475505452243994499203144406756052692789829481237313413437224332089488972
Line 334, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003359281 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x656b5454, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10003359281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
18.spi_host_idlecsbactive.90222784519646119864454603312982208071275902250779482479781789180820108343975
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10019851844 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5ef55914, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10019851844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=38) has 1 failures:
18.spi_host_spien.87674614065615068368227282515110477281109816553429702066164827421233586823930
Line 473, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_spien/latest/run.log
UVM_FATAL @ 10270072362 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5c966954, Comparison=CompareOpEq, exp_data=0x1, call_count=38)
UVM_INFO @ 10270072362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
21.spi_host_stress_all.15604577404365581766937216935895476883627745200873654216309833990670784680209
Line 427, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10097171115 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf0e2c254, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10097171115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
22.spi_host_stress_all.37238086159614121479572236380848741981001705937667553935729660791708421246418
Line 413, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10012892658 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7e78ba94, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10012892658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=43) has 1 failures:
23.spi_host_sw_reset.42965281445346890276938692684703743419832270676986129304310539573267777105296
Line 497, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10067440022 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf53c3754, Comparison=CompareOpEq, exp_data=0x0, call_count=43)
UVM_INFO @ 10067440022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
27.spi_host_sw_reset.2069540123930891974488603248672926141478739266849172694322803138683632347129
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10043621252 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9d3a5614, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
UVM_INFO @ 10043621252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
30.spi_host_sw_reset.59208242339094790218456232849690394524066635122503866780175538426761994136531
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15146329358 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3dc5d894, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 15146329358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
32.spi_host_smoke.69221186851269095726532628013699983450915713317017604888974620020450416964680
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_smoke/latest/run.log
UVM_FATAL @ 15224021538 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x19facf94, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
UVM_INFO @ 15224021538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=85) has 1 failures:
33.spi_host_status_stall.36484235516049138853942463713533848214240302817507451362253371983149382149099
Line 933, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_status_stall/latest/run.log
UVM_FATAL @ 14191408651 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x82e0dd94, Comparison=CompareOpEq, exp_data=0x1, call_count=85)
UVM_INFO @ 14191408651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=82) has 1 failures:
44.spi_host_status_stall.49176779332852296852604854160082970743761852699016108571774669393351486107206
Line 917, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log
UVM_FATAL @ 21481448087 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x85dde14, Comparison=CompareOpEq, exp_data=0x1, call_count=82)
UVM_INFO @ 21481448087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
49.spi_host_sw_reset.9505118107955582405461196934556816797323612580706663896406802396446807484202
Line 336, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10038147361 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x720ac494, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10038147361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---