a47820eb4c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 16.250m | 15.001ms | 35 | 50 | 70.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 17.000s | 55.472us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 7.000s | 20.245us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 1.538ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 83.134us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 29.065us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 7.000s | 20.245us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 83.134us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 7.000s | 58.321us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 221.979us | 5 | 5 | 100.00 |
| V1 | TOTAL | 100 | 115 | 86.96 | |||
| V2 | performance | spi_host_performance | 13.000s | 36.238us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.217m | 23.954ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 10.000s | 30.481us | 50 | 50 | 100.00 | ||
| spi_host_event | 15.133m | 175.358ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.367m | 10.001ms | 38 | 50 | 76.00 |
| V2 | speed | spi_host_speed | 11.367m | 10.001ms | 38 | 50 | 76.00 |
| V2 | chip_select_timing | spi_host_speed | 11.367m | 10.001ms | 38 | 50 | 76.00 |
| V2 | sw_reset | spi_host_sw_reset | 9.183m | 15.008ms | 34 | 50 | 68.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 12.000s | 86.960us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.367m | 10.001ms | 38 | 50 | 76.00 |
| V2 | full_cycle | spi_host_speed | 11.367m | 10.001ms | 38 | 50 | 76.00 |
| V2 | duplex | spi_host_smoke | 16.250m | 15.001ms | 35 | 50 | 70.00 |
| V2 | tx_rx_only | spi_host_smoke | 16.250m | 15.001ms | 35 | 50 | 70.00 |
| V2 | stress_all | spi_host_stress_all | 17.733m | 15.214ms | 41 | 50 | 82.00 |
| V2 | spien | spi_host_spien | 16.333m | 15.001ms | 36 | 50 | 72.00 |
| V2 | stall | spi_host_status_stall | 7.600m | 10.348ms | 35 | 50 | 70.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 13.383m | 200.000ms | 38 | 50 | 76.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 3.217m | 23.954ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 12.000s | 27.206us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 12.000s | 24.648us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 9.000s | 135.209us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 9.000s | 135.209us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 17.000s | 55.472us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 20.245us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 83.134us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 16.651us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 17.000s | 55.472us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 20.245us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 83.134us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 16.651us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 612 | 690 | 88.70 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 13.000s | 176.180us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 8.000s | 174.882us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 13.000s | 176.180us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 53.400m | 100.003ms | 3 | 10 | 30.00 | |
| TOTAL | 740 | 840 | 88.10 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.84 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 29 failures:
0.spi_host_stress_all.98296064863084117825275442586827939394345601608952897585228366587611644727467
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001949884 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfa3460d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001949884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_host_stress_all.87007270281901997830196847034235261279543213313371021545189793038647675045927
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001703271 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6c4123d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001703271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
3.spi_host_upper_range_clkdiv.47852330942062937132575528697968910551625860362029995125456685768764928777389
Line 303, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004294050 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4e324b94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100004294050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_upper_range_clkdiv.73333316439915875542031644287550754700570770650416551585349303833821108694085
Line 313, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003104188 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8674714, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003104188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
6.spi_host_smoke.13151140427492021773985708312875874117096669272638625122682906969480694862707
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001619071 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcdbdd554, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001619071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_smoke.36037998303612709238749332041461196924138625911131129931973747927940436065453
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
UVM_FATAL @ 15005239758 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x26a5f214, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15005239758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
10.spi_host_speed.113220490773181682062595707029591530852666447278849636313869483060911005372618
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_speed/latest/run.log
UVM_FATAL @ 10003099452 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5bd75914, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003099452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_speed.44898475052941631645756516097485118682186222157182319614302425430634989831095
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_speed/latest/run.log
UVM_FATAL @ 10001059638 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x29222ad4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001059638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
18.spi_host_spien.93581921887897504642132786031418797292994961759325484441753751187140388353013
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_spien/latest/run.log
UVM_FATAL @ 10002497177 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x47625054, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002497177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_host_spien.12162935403929194735404963302108326836173141028160889967611637420169670250789
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_spien/latest/run.log
UVM_FATAL @ 10001090250 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x62c110d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001090250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 16 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
6.spi_host_upper_range_clkdiv.64771696303367345852189530286130102618187383950835288078816065702425140563574
Line 307, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100006435648 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7a649a94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100006435648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_upper_range_clkdiv.55552305894643002580732236455424356937541254175394254443367195181931888324122
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002564861 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf7630ed4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100002564861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 5 failures.
7.spi_host_smoke.36394045216506162912142222423497074231725600742404409207498010928066086387019
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000821376 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc0117514, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000821376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_host_smoke.83829121151383857194309502873747286084498932043467676360807686667196107413039
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_smoke/latest/run.log
UVM_FATAL @ 15005286110 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x84f98c54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15005286110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_speed has 5 failures.
8.spi_host_speed.8851849723752150765111751452843742197015234397299905563178090964760653221979
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_speed/latest/run.log
UVM_FATAL @ 10001095449 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb6999e14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001095449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_speed.93729153224862706321641577310797307638575315528865680801162550471915832692627
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_speed/latest/run.log
UVM_FATAL @ 10008475752 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2654c914, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10008475752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_spien has 3 failures.
12.spi_host_spien.45103821897978356334005716717639643949269738036125515961899410679791493992125
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_spien/latest/run.log
UVM_FATAL @ 15001351060 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9ecfcbd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001351060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_spien.86124734532408907706997257862225386017751883465472090936873252808430706535863
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_spien/latest/run.log
UVM_FATAL @ 10004279086 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x33443294, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004279086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_stress_all has 1 failures.
26.spi_host_stress_all.73866707060957015123020906862528448419476774879110587335017598673232632490695
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001813323 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x57fe5bd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001813323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 4 failures:
1.spi_host_idlecsbactive.105607495321110716923132214288146633493751041701680892524605608162870112775066
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10011778312 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x98a26214, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10011778312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_idlecsbactive.98724043613798869221212227978502514379157058558677283896888195567351232655560
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10009322648 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x14be9694, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10009322648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 4 failures:
8.spi_host_status_stall.53426523209149829825901551532265280304527969524969761662036657218042132962187
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15008702753 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1ce977d4, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 15008702753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.spi_host_status_stall.68362858722921871330564485470865255298089499590600533954508696037276231425788
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003185249 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa7ffdad4, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10003185249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
37.spi_host_sw_reset.43508110541339137099461689392352801638713662213564990102445288414916324913658
Line 342, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15009812371 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x72f6d194, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 15009812371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 3 failures:
1.spi_host_sw_reset.108049203335897025153983841487164418556809814721229595729054960844526291615697
Line 334, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10007561464 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x351df4d4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10007561464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_host_sw_reset.19446396158493545640142453203106484405381425773948512420389381256622319229431
Line 334, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10010754586 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xca0b3794, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10010754586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 2 failures:
0.spi_host_sw_reset.929738631131750173929062563939781591723414563363920353922257520744260473779
Line 326, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15007507207 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x655e6754, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 15007507207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.spi_host_sw_reset.39373762078371666054285021093176419744899399505477725973831293931927232436033
Line 326, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003942452 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa8571a54, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10003942452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 2 failures:
Test spi_host_spien has 1 failures.
8.spi_host_spien.106023802938496961612599687597244491524355687650504573464986055135839829266836
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_spien/latest/run.log
UVM_FATAL @ 10021722998 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xeca5f894, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10021722998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
41.spi_host_status_stall.47455004335518903585903563018593105221976452234079229542420172697774639440557
Line 439, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15394254062 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x789eaa14, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 15394254062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
11.spi_host_idlecsbactive.111223464863497689041602518668180194213810754306466966647272942132837123890102
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.spi_host_idlecsbactive.80587116455058110618153710801294805236001770927575752167881217192475350947313
Line 403, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
21.spi_host_sw_reset.72819919345696711114585369840706038241788377612057261776469405126180188191441
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15003615717 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8c2af0d4, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 15003615717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_sw_reset.68703913256688559618768682943198385983881306216405268319884655599681330040834
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15004520532 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x67d92ad4, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 15004520532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
28.spi_host_sw_reset.9771561589274630375631919823410241936962857791474677431695149974961464628075
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10004196859 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x57fb28d4, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10004196859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.spi_host_sw_reset.30985076779931796042035000518427878091356818279270976495835428312021999042308
Line 370, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001729412 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5001cf94, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10001729412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:
29.spi_host_status_stall.46394529204502772261879888881988424008403928097440588174795443667250939260361
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
UVM_ERROR @ 4190332 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4190332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.spi_host_status_stall.66028312882484411696502811859984874754327538363723000657886514102058844453852
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_status_stall/latest/run.log
UVM_ERROR @ 1649637 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1649637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
1.spi_host_upper_range_clkdiv.59250179416818905181837830051664214990879937502601111840904510871142501989386
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:374180e5-0110-44a3-b94f-c2903fc5dc2c
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
2.spi_host_idlecsbactive.105887722480163853628638049080568093538744014412247355489492117869201810230823
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002914376 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf622ca54, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10002914376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=34) has 1 failures:
3.spi_host_speed.19792061136392322319400412812257460694027511394859120017936163074155702989643
Line 437, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_speed/latest/run.log
UVM_FATAL @ 10065941485 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfea1ce54, Comparison=CompareOpEq, exp_data=0x1, call_count=34)
UVM_INFO @ 10065941485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=42) has 1 failures:
3.spi_host_stress_all.25552913452144366801695031286390470755947773257475106950062884440372659733012
Line 487, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_stress_all/latest/run.log
UVM_FATAL @ 25230828611 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7d6d0594, Comparison=CompareOpEq, exp_data=0x1, call_count=42)
UVM_INFO @ 25230828611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
4.spi_host_status_stall.14870665578571935224275927509524521474267080827638298278192539517665588286647
Line 435, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15546034413 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x30a9f8d4, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 15546034413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
5.spi_host_status_stall.16748465325170625385408351609165655401926933347379762444805374391585478031386
Line 415, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10019750760 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xeede5ad4, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 10019750760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=29) has 1 failures:
11.spi_host_spien.3844994855696780028068200275805509088261161697850773633591131253789578501677
Line 445, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_spien/latest/run.log
UVM_FATAL @ 10035368596 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xdf3ff194, Comparison=CompareOpEq, exp_data=0x1, call_count=29)
UVM_INFO @ 10035368596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=32) has 1 failures:
12.spi_host_stress_all.307374341754779724904398666885919961993011388415590721568918444676985926777
Line 469, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15114880311 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb3556854, Comparison=CompareOpEq, exp_data=0x0, call_count=32)
UVM_INFO @ 15114880311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=31) has 1 failures:
13.spi_host_sw_reset.114372651550270519472029614164578254204335123709161867404578038728552127178517
Line 429, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10023572466 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x234734d4, Comparison=CompareOpEq, exp_data=0x1, call_count=31)
UVM_INFO @ 10023572466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
13.spi_host_stress_all.58768382087360742461700643713981146098748767139285090964897035521578533048544
Line 406, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15038271271 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x963afb54, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 15038271271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
19.spi_host_stress_all.12788538658723061379682081746751640525950122488269719201689763880843510714194
Line 419, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10014216257 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6e7ffbd4, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10014216257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 1 failures:
20.spi_host_status_stall.63919237226680629968796836813812542465005252711472509886284616195157431479264
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log
UVM_ERROR @ 2995491 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 2995491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
27.spi_host_sw_reset.80923401671032507615913509551931601736187596376498126919426819329931049381695
Line 360, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10039152752 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6175fa54, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10039152752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
27.spi_host_idlecsbactive.55404931349472273058644130377027161213596843984447759605499147786111057971981
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
27.spi_host_stress_all.45738113665697313631923364327340517396169744543893354218819614534247009310233
Line 426, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15214236839 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe72e7c94, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 15214236839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
27.spi_host_spien.21234714620773553452286535442873288150622558604720312130757831612384636931997
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_spien/latest/run.log
UVM_FATAL @ 10008192266 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3da3c8d4, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10008192266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=83) has 1 failures:
28.spi_host_status_stall.78740361417638764928835098517763425927066576306815939417284976572630010101507
Line 929, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10347819809 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa888ead4, Comparison=CompareOpEq, exp_data=0x1, call_count=83)
UVM_INFO @ 10347819809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
29.spi_host_idlecsbactive.99648149382573354800589862898361918734453269984705044546352667390957475001600
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10015139268 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x505dd594, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10015139268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
31.spi_host_status_stall.83790414008714302466052822115714667308691066237372129319931692731240473991575
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10012795272 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc61f4f54, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10012795272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
31.spi_host_idlecsbactive.67824951787476242611781827447130881718826798525134393559015697719020733643110
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10009606000 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb26a4654, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10009606000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=31) has 1 failures:
34.spi_host_speed.39575654809170180875339154739407880821115825117311942633124806708786814723873
Line 407, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_speed/latest/run.log
UVM_FATAL @ 10042273150 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2e6e3514, Comparison=CompareOpEq, exp_data=0x1, call_count=31)
UVM_INFO @ 10042273150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
36.spi_host_idlecsbactive.21603777495405531028688014898546961279363284695930219723554731135020839614156
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10005562681 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe3a87bd4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10005562681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=44) has 1 failures:
38.spi_host_sw_reset.111905530302089944574824331779665139188729725418079260406504241763952180838482
Line 504, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10308818860 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9dbe4114, Comparison=CompareOpEq, exp_data=0x1, call_count=44)
UVM_INFO @ 10308818860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=78) has 1 failures:
38.spi_host_status_stall.39806547750306440661574540937490205555461259183588515402569584676387762850488
Line 873, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10174623265 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa15f2a94, Comparison=CompareOpEq, exp_data=0x1, call_count=78)
UVM_INFO @ 10174623265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=81) has 1 failures:
42.spi_host_status_stall.52824584661983908786274603850428051213890207529210826614405974199071894302697
Line 927, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15008011265 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd9ebb3d4, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
UVM_INFO @ 15008011265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
43.spi_host_sw_reset.95015408139025425702558928369057870673230137186760956628917188876534131988125
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10016796760 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1e959714, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10016796760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
44.spi_host_sw_reset.78447892972620860268424097850608611084294004646947782235312673035201696103331
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10009481920 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf0137354, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10009481920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=85) has 1 failures:
44.spi_host_status_stall.10419199219726853006364802245852159389791048505762969489557268849034799048010
Line 939, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10315405834 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x92feca94, Comparison=CompareOpEq, exp_data=0x1, call_count=85)
UVM_INFO @ 10315405834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=39) has 1 failures:
46.spi_host_smoke.1637687927269813945409805783132461887611542157951214853171304936899427419070
Line 437, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_smoke/latest/run.log
UVM_FATAL @ 16676349309 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfa078114, Comparison=CompareOpEq, exp_data=0x1, call_count=39)
UVM_INFO @ 16676349309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
46.spi_host_idlecsbactive.20529426845205146891330353675353357341601505367740299350747975952028596102109
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004807833 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x493a8cd4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10004807833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
49.spi_host_sw_reset.114593306872363648188850470548776387467117031966758422575309485415602011134341
Line 352, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15015319874 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe92bfcd4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 15015319874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
49.spi_host_status_stall.107950682363480394459288949788920557778658731714015319845177764189898590328889
Line 413, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10009818867 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe5cd7854, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10009818867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---