SPI_HOST Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 16.250m 15.001ms 35 50 70.00
V1 csr_hw_reset spi_host_csr_hw_reset 17.000s 55.472us 5 5 100.00
V1 csr_rw spi_host_csr_rw 7.000s 20.245us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 1.538ms 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 83.134us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 29.065us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 7.000s 20.245us 20 20 100.00
spi_host_csr_aliasing 3.000s 83.134us 5 5 100.00
V1 mem_walk spi_host_mem_walk 7.000s 58.321us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 221.979us 5 5 100.00
V1 TOTAL 100 115 86.96
V2 performance spi_host_performance 13.000s 36.238us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.217m 23.954ms 50 50 100.00
spi_host_error_cmd 10.000s 30.481us 50 50 100.00
spi_host_event 15.133m 175.358ms 50 50 100.00
V2 clock_rate spi_host_speed 11.367m 10.001ms 38 50 76.00
V2 speed spi_host_speed 11.367m 10.001ms 38 50 76.00
V2 chip_select_timing spi_host_speed 11.367m 10.001ms 38 50 76.00
V2 sw_reset spi_host_sw_reset 9.183m 15.008ms 34 50 68.00
V2 passthrough_mode spi_host_passthrough_mode 12.000s 86.960us 50 50 100.00
V2 cpol_cpha spi_host_speed 11.367m 10.001ms 38 50 76.00
V2 full_cycle spi_host_speed 11.367m 10.001ms 38 50 76.00
V2 duplex spi_host_smoke 16.250m 15.001ms 35 50 70.00
V2 tx_rx_only spi_host_smoke 16.250m 15.001ms 35 50 70.00
V2 stress_all spi_host_stress_all 17.733m 15.214ms 41 50 82.00
V2 spien spi_host_spien 16.333m 15.001ms 36 50 72.00
V2 stall spi_host_status_stall 7.600m 10.348ms 35 50 70.00
V2 Idlecsbactive spi_host_idlecsbactive 13.383m 200.000ms 38 50 76.00
V2 data_fifo_status spi_host_overflow_underflow 3.217m 23.954ms 50 50 100.00
V2 alert_test spi_host_alert_test 12.000s 27.206us 50 50 100.00
V2 intr_test spi_host_intr_test 12.000s 24.648us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 9.000s 135.209us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 9.000s 135.209us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 17.000s 55.472us 5 5 100.00
spi_host_csr_rw 7.000s 20.245us 20 20 100.00
spi_host_csr_aliasing 3.000s 83.134us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 16.651us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 17.000s 55.472us 5 5 100.00
spi_host_csr_rw 7.000s 20.245us 20 20 100.00
spi_host_csr_aliasing 3.000s 83.134us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 16.651us 20 20 100.00
V2 TOTAL 612 690 88.70
V2S tl_intg_err spi_host_tl_intg_err 13.000s 176.180us 20 20 100.00
spi_host_sec_cm 8.000s 174.882us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 13.000s 176.180us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 53.400m 100.003ms 3 10 30.00
TOTAL 740 840 88.10

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results