4877b481e8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 16.267m | 15.001ms | 38 | 50 | 76.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 19.477us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 8.000s | 167.452us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 319.715us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 18.542us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 8.000s | 35.144us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 8.000s | 167.452us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 18.542us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 36.698us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 25.177us | 5 | 5 | 100.00 |
| V1 | TOTAL | 103 | 115 | 89.57 | |||
| V2 | performance | spi_host_performance | 17.000s | 31.234us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.133m | 2.795ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 8.000s | 43.986us | 50 | 50 | 100.00 | ||
| spi_host_event | 9.833m | 129.128ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 12.167m | 10.001ms | 36 | 50 | 72.00 |
| V2 | speed | spi_host_speed | 12.167m | 10.001ms | 36 | 50 | 72.00 |
| V2 | chip_select_timing | spi_host_speed | 12.167m | 10.001ms | 36 | 50 | 72.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.350m | 15.003ms | 36 | 50 | 72.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 8.000s | 5.557ms | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 12.167m | 10.001ms | 36 | 50 | 72.00 |
| V2 | full_cycle | spi_host_speed | 12.167m | 10.001ms | 36 | 50 | 72.00 |
| V2 | duplex | spi_host_smoke | 16.267m | 15.001ms | 38 | 50 | 76.00 |
| V2 | tx_rx_only | spi_host_smoke | 16.267m | 15.001ms | 38 | 50 | 76.00 |
| V2 | stress_all | spi_host_stress_all | 12.917m | 36.449ms | 41 | 50 | 82.00 |
| V2 | spien | spi_host_spien | 12.050m | 10.001ms | 34 | 50 | 68.00 |
| V2 | stall | spi_host_status_stall | 8.017m | 10.034ms | 41 | 50 | 82.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 12.033m | 15.003ms | 35 | 50 | 70.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.133m | 2.795ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 12.000s | 19.564us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 13.000s | 34.596us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 13.000s | 292.444us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 13.000s | 292.444us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 19.477us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 8.000s | 167.452us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 18.542us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 27.852us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 19.477us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 8.000s | 167.452us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 18.542us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 27.852us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 613 | 690 | 88.84 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 13.000s | 706.442us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 7.000s | 59.388us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 13.000s | 706.442us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 41.083m | 100.003ms | 5 | 10 | 50.00 | |
| TOTAL | 746 | 840 | 88.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.77 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 26 failures:
Test spi_host_spien has 9 failures.
2.spi_host_spien.50565252454066466294053041293734800085648619059108795086354629753930602462199
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_spien/latest/run.log
UVM_FATAL @ 10004117721 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe9927094, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004117721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_host_spien.3900801472213269821752942004639697651765281630055498592777873407343221237989
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_spien/latest/run.log
UVM_FATAL @ 10001179920 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4f0fcc54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001179920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test spi_host_smoke has 6 failures.
5.spi_host_smoke.88006299954154603116960561769770932987191862911138751282390210660532359024924
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
UVM_FATAL @ 15002852694 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf5096494, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002852694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_smoke.26139394817525355323574352970994423350149591130465248759198619273308298815771
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_smoke/latest/run.log
UVM_FATAL @ 15004204896 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfa43de14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15004204896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_upper_range_clkdiv has 2 failures.
6.spi_host_upper_range_clkdiv.4786738033257816191081498337640269481540354325302221299922608522098766910326
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005430045 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7e5dcb54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100005430045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_upper_range_clkdiv.14824756954836225078031133745337890052760322558823320774951979953752802894886
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100000732687 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1e9dcd14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100000732687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 8 failures.
12.spi_host_speed.107014647125719756910900813620002020366552061361829911492063441806559293892889
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_speed/latest/run.log
UVM_FATAL @ 10000954489 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x357ba014, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000954489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_host_speed.57273692068752406392414384972622285207341338400010735940303593004132400254445
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_speed/latest/run.log
UVM_FATAL @ 10000994561 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x811831d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000994561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test spi_host_stress_all has 1 failures.
44.spi_host_stress_all.22470853865851755560155735067392087931329411076840345837972488784355395119317
Line 336, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15002010609 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbfd93554, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002010609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 14 failures:
0.spi_host_stress_all.28202633153232613869698498356782464682548858911949033308003429412650089845443
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10003485449 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x26c28514, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003485449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_stress_all.15904787718139039536396094320917457321650943933361228319739855163419041484209
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15004265028 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1da988d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15004265028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
9.spi_host_spien.34876914025178791528260908553540214372649126194524459550594534280410520303238
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_spien/latest/run.log
UVM_FATAL @ 10002233721 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa8ba9194, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002233721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.spi_host_spien.5733396921168321440497552977702597079999407698344195391448372188611836458290
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_spien/latest/run.log
UVM_FATAL @ 10001735643 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa6ac67d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001735643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
10.spi_host_smoke.94777676242680692703293778852525341762955934197195230747955236881329335296136
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001773941 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5f494ad4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001773941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_smoke.110703018573493052601643604463467133668038149874297633103957178936272680558467
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001777225 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x344a254, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001777225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
29.spi_host_speed.71792761266023980481285227321761717586374585375608963368073156520412540772495
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_speed/latest/run.log
UVM_FATAL @ 10005352696 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6526c0d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10005352696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_host_speed.84404830798035596851181040146754443724356597407094937964537647702041895193359
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_speed/latest/run.log
UVM_FATAL @ 10001718687 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6d827a54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001718687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 8 failures:
5.spi_host_idlecsbactive.20779561175887575189901889091760367621913534135983887587084907469648927348471
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10007893094 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcbaaf3d4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10007893094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_idlecsbactive.48287505577323605743555668275921177932913204630161734798684983190534831861127
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15004500648 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4b0e2654, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 15004500648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 3 failures:
6.spi_host_idlecsbactive.8898067980561828514375477502410915316457441084945065026110843464675006004487
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10003075803 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x655e8e54, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10003075803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_host_idlecsbactive.4510770678683848383844851937030796116158061284725690128815291524618981153424
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002346617 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5a2a0754, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10002346617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 3 failures:
Test spi_host_sw_reset has 2 failures.
26.spi_host_sw_reset.103879644968564050421465462326175212593562324475198918319425528418699281125778
Line 376, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15169003825 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x91513754, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 15169003825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_sw_reset.77909571736284626501593228410605646017366096245585673761162776657721977157073
Line 368, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002246388 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9c993b94, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10002246388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
36.spi_host_spien.61518373116581442104366677267606118880885808055978302344144476581406254130005
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_spien/latest/run.log
UVM_FATAL @ 10057818855 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x42689b14, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10057818855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 2 failures:
5.spi_host_sw_reset.43301952957923994656294875924393837173151196010695646370264987278462996912633
Line 322, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15002505288 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9af90d94, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 15002505288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_sw_reset.72136295818751307298220471231795476772414547838513883554873211989568124391247
Line 340, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10004030557 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe2c7f714, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10004030557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
7.spi_host_sw_reset.106458211211508098841362733249028189543879533810172817176019288402200228124625
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10013343567 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe53f40d4, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10013343567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.spi_host_sw_reset.13535191212780333264677223396737991734526653993452225886687452380200272453631
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15016760443 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x92a3c694, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 15016760443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
27.spi_host_idlecsbactive.10809956222103460274330472673814016849669052856472786128554761219944274938597
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.spi_host_idlecsbactive.93371637231338288567968229120190339493298914935016186599418533950936252191011
Line 403, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
32.spi_host_sw_reset.18369859571353095219439347522109723664813533379277370510182642991191916779858
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10005665277 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8fe91214, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10005665277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.spi_host_sw_reset.70066465304666711271730521830979779032279412498386475676767186854359718574758
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15007107563 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa93aa8d4, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 15007107563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
0.spi_host_idlecsbactive.58922081013193159041738558144513858373095637738842007139640524133083456268904
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10015889857 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd97d3c54, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10015889857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
1.spi_host_upper_range_clkdiv.35914378046680649774935461954924225941915861907175160692323612570056673382801
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003428605 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x39cbadd4, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 100003428605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
1.spi_host_sw_reset.65067167650847678094927176758997025292573269988766962373339217785306690252045
Line 336, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10007283101 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x94a12494, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10007283101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
1.spi_host_status_stall.58203567662992727080030145069750607251014918334770272009732026840656248553233
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10008196278 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb096e454, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10008196278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
3.spi_host_sw_reset.54863660180792104522593543979133958294455841653026723554909328179385442281301
Line 314, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10017427244 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x912c654, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10017427244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
4.spi_host_upper_range_clkdiv.36197985592846140492174211024286523485233209577070116726447696422739304820628
Line 323, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100011826786 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc0c7794, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 100011826786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
4.spi_host_spien.79075038842722209542588194572427338934413403024148106497496466307066042044267
Line 379, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_spien/latest/run.log
UVM_FATAL @ 10579850496 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd73c0354, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10579850496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
5.spi_host_upper_range_clkdiv.46305767056997979152941686001082974156719980020062971466495739088557254824981
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:896d357a-b333-4d41-85ad-7f5cc07434f6
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=88) has 1 failures:
5.spi_host_status_stall.105227365259239471079965913685888625326704214150223868334771734839831786993463
Line 955, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log
UVM_FATAL @ 18745169101 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb1151b54, Comparison=CompareOpEq, exp_data=0x1, call_count=88)
UVM_INFO @ 18745169101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
5.spi_host_stress_all.491636749768572793458424192871137210193106194369108140038960432886049472917
Line 468, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15218974761 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x15e9d394, Comparison=CompareOpEq, exp_data=0x0, call_count=30)
UVM_INFO @ 15218974761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_scoreboard.sv:569) scoreboard [scoreboard] Didn't check all segments - expected * actual * has 1 failures:
7.spi_host_idlecsbactive.77355871083255681392234365442718901284846340816596484984573170421101045183806
Line 411, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 30696253 ps: (spi_host_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Didn't check all segments - expected 6 actual 5
UVM_INFO @ 30696253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
9.spi_host_smoke.41113652657899626628168923990612636119659378864762985715340481477645223468255
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_smoke/latest/run.log
UVM_FATAL @ 10034682563 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5e08aa94, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10034682563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=107) has 1 failures:
9.spi_host_speed.90318283446825914067784776635385621142551437016139697905798232073760385015523
Line 873, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_speed/latest/run.log
UVM_FATAL @ 10345718732 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x24768094, Comparison=CompareOpEq, exp_data=0x0, call_count=107)
UVM_INFO @ 10345718732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
9.spi_host_status_stall.47724580471270773259425767885432256461121152818076714483187134479172876163029
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10002716558 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x18b1e294, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10002716558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
10.spi_host_status_stall.39657041386714228566206253101112276753208943733153687837779705370546405431034
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10087937176 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd33de194, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10087937176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
10.spi_host_stress_all.52681198777132189372564934271477687873610401095417614840587001455402166915991
Line 421, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10042845031 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x82808f14, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10042845031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
12.spi_host_sw_reset.18896627057198338269067264964909642911119514318736431857237551089629001138181
Line 421, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10181100071 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb434f8d4, Comparison=CompareOpEq, exp_data=0x1, call_count=27)
UVM_INFO @ 10181100071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
25.spi_host_status_stall.37778191457395870797682105296259399810746509663934896847088827191156635997398
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10034294018 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8c8602d4, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 10034294018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=34) has 1 failures:
28.spi_host_speed.70204098269945368119075168191718088148030745306272801756012963340739048372942
Line 423, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_speed/latest/run.log
UVM_FATAL @ 10010695519 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe1925854, Comparison=CompareOpEq, exp_data=0x1, call_count=34)
UVM_INFO @ 10010695519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
32.spi_host_spien.97430979611023784775858026556269542013596713254709739408093100022770896318250
Line 417, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_spien/latest/run.log
UVM_FATAL @ 15663250647 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfaafef54, Comparison=CompareOpEq, exp_data=0x1, call_count=25)
UVM_INFO @ 15663250647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
33.spi_host_speed.81572303224936617768046038350857101397702265514230942010214164512314564636213
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_speed/latest/run.log
UVM_FATAL @ 10063250474 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x29562d4, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10063250474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
38.spi_host_status_stall.98025091112932051881634145045494086337805374487761047079639823778689273022592
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10002065409 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5e534b94, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10002065409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
38.spi_host_stress_all.28098890080310271463539443769931014140429698173024702402725807017435869134278
Line 449, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_stress_all/latest/run.log
UVM_FATAL @ 36449028803 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4cf3c194, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
UVM_INFO @ 36449028803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:
39.spi_host_status_stall.34279877382018282416734040922051854546961511175547682548867099035354510780113
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_status_stall/latest/run.log
UVM_ERROR @ 4011419 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4011419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
40.spi_host_spien.7986819875223415282106269718432501040806282649183025050752548556777205836295
Line 417, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_spien/latest/run.log
UVM_FATAL @ 10130608364 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1dcec554, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
UVM_INFO @ 10130608364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
43.spi_host_status_stall.37562915452772553897182101065435698198274091507808347751508716092905935038703
Line 411, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10018985150 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc2d00254, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10018985150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
43.spi_host_stress_all.9136061498761888566355913526341544281270701373763043287381255664865623708990
Line 413, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10049290506 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe28ca694, Comparison=CompareOpEq, exp_data=0x0, call_count=30)
UVM_INFO @ 10049290506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
45.spi_host_sw_reset.20600477666104233960263166259319927805151189511535437282228237184584663284167
Line 346, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10014385130 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9147d514, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10014385130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 1 failures:
45.spi_host_status_stall.73337582947889987236200567613887246334992317685806746097520202475531353478400
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_status_stall/latest/run.log
UVM_ERROR @ 1681148 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 1681148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
46.spi_host_sw_reset.34638399482986922925104762266697968309131951864803064840646951736611678258360
Line 312, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15006539666 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x63b41714, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 15006539666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
46.spi_host_stress_all.76759177776117324212068278572413562664929797730397813685327283683509314969094
Line 432, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15184791130 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x54aa3d94, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 15184791130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
49.spi_host_sw_reset.112415578271700165696356066373001819625195581762014466413132248550200433847059
Line 342, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10006503591 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2a737ed4, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10006503591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---