SPI_HOST Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 16.267m 15.001ms 38 50 76.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 19.477us 5 5 100.00
V1 csr_rw spi_host_csr_rw 8.000s 167.452us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 319.715us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 18.542us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 8.000s 35.144us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 8.000s 167.452us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.542us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 36.698us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 25.177us 5 5 100.00
V1 TOTAL 103 115 89.57
V2 performance spi_host_performance 17.000s 31.234us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.133m 2.795ms 50 50 100.00
spi_host_error_cmd 8.000s 43.986us 50 50 100.00
spi_host_event 9.833m 129.128ms 50 50 100.00
V2 clock_rate spi_host_speed 12.167m 10.001ms 36 50 72.00
V2 speed spi_host_speed 12.167m 10.001ms 36 50 72.00
V2 chip_select_timing spi_host_speed 12.167m 10.001ms 36 50 72.00
V2 sw_reset spi_host_sw_reset 10.350m 15.003ms 36 50 72.00
V2 passthrough_mode spi_host_passthrough_mode 8.000s 5.557ms 50 50 100.00
V2 cpol_cpha spi_host_speed 12.167m 10.001ms 36 50 72.00
V2 full_cycle spi_host_speed 12.167m 10.001ms 36 50 72.00
V2 duplex spi_host_smoke 16.267m 15.001ms 38 50 76.00
V2 tx_rx_only spi_host_smoke 16.267m 15.001ms 38 50 76.00
V2 stress_all spi_host_stress_all 12.917m 36.449ms 41 50 82.00
V2 spien spi_host_spien 12.050m 10.001ms 34 50 68.00
V2 stall spi_host_status_stall 8.017m 10.034ms 41 50 82.00
V2 Idlecsbactive spi_host_idlecsbactive 12.033m 15.003ms 35 50 70.00
V2 data_fifo_status spi_host_overflow_underflow 2.133m 2.795ms 50 50 100.00
V2 alert_test spi_host_alert_test 12.000s 19.564us 50 50 100.00
V2 intr_test spi_host_intr_test 13.000s 34.596us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 13.000s 292.444us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 13.000s 292.444us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 19.477us 5 5 100.00
spi_host_csr_rw 8.000s 167.452us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.542us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 27.852us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 19.477us 5 5 100.00
spi_host_csr_rw 8.000s 167.452us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.542us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 27.852us 20 20 100.00
V2 TOTAL 613 690 88.84
V2S tl_intg_err spi_host_tl_intg_err 13.000s 706.442us 20 20 100.00
spi_host_sec_cm 7.000s 59.388us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 13.000s 706.442us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 41.083m 100.003ms 5 10 50.00
TOTAL 746 840 88.81

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.77 95.70 100.00 95.07 90.87

Failure Buckets

Past Results