SPI_HOST Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 11.367m 15.156ms 38 50 76.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 18.599us 5 5 100.00
V1 csr_rw spi_host_csr_rw 7.000s 52.617us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 403.938us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 48.776us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 7.000s 47.645us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 7.000s 52.617us 20 20 100.00
spi_host_csr_aliasing 3.000s 48.776us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 26.629us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 26.047us 5 5 100.00
V1 TOTAL 103 115 89.57
V2 performance spi_host_performance 7.000s 58.801us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 1.500m 3.620ms 50 50 100.00
spi_host_error_cmd 8.000s 52.321us 50 50 100.00
spi_host_event 19.167m 111.907ms 50 50 100.00
V2 clock_rate spi_host_speed 11.567m 10.001ms 40 50 80.00
V2 speed spi_host_speed 11.567m 10.001ms 40 50 80.00
V2 chip_select_timing spi_host_speed 11.567m 10.001ms 40 50 80.00
V2 sw_reset spi_host_sw_reset 11.550m 15.002ms 34 50 68.00
V2 passthrough_mode spi_host_passthrough_mode 8.000s 190.267us 50 50 100.00
V2 cpol_cpha spi_host_speed 11.567m 10.001ms 40 50 80.00
V2 full_cycle spi_host_speed 11.567m 10.001ms 40 50 80.00
V2 duplex spi_host_smoke 11.367m 15.156ms 38 50 76.00
V2 tx_rx_only spi_host_smoke 11.367m 15.156ms 38 50 76.00
V2 stress_all spi_host_stress_all 17.633m 15.002ms 39 50 78.00
V2 spien spi_host_spien 7.850m 15.003ms 43 50 86.00
V2 stall spi_host_status_stall 11.850m 15.879ms 33 50 66.00
V2 Idlecsbactive spi_host_idlecsbactive 13.233m 200.000ms 36 50 72.00
V2 data_fifo_status spi_host_overflow_underflow 1.500m 3.620ms 50 50 100.00
V2 alert_test spi_host_alert_test 7.000s 47.479us 50 50 100.00
V2 intr_test spi_host_intr_test 8.000s 52.457us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 9.000s 39.059us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 9.000s 39.059us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 18.599us 5 5 100.00
spi_host_csr_rw 7.000s 52.617us 20 20 100.00
spi_host_csr_aliasing 3.000s 48.776us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 69.019us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 18.599us 5 5 100.00
spi_host_csr_rw 7.000s 52.617us 20 20 100.00
spi_host_csr_aliasing 3.000s 48.776us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 69.019us 20 20 100.00
V2 TOTAL 615 690 89.13
V2S tl_intg_err spi_host_tl_intg_err 8.000s 88.156us 20 20 100.00
spi_host_sec_cm 8.000s 66.915us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 8.000s 88.156us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 58.483m 100.001ms 1 10 10.00
TOTAL 744 840 88.57

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.00 90.92 83.18 92.77 89.69 95.70 100.00 95.07 90.87

Failure Buckets

Past Results