eca25c0ff8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 11.367m | 15.156ms | 38 | 50 | 76.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 2.000s | 18.599us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 7.000s | 52.617us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 403.938us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 48.776us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 7.000s | 47.645us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 7.000s | 52.617us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 48.776us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 3.000s | 26.629us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 2.000s | 26.047us | 5 | 5 | 100.00 |
| V1 | TOTAL | 103 | 115 | 89.57 | |||
| V2 | performance | spi_host_performance | 7.000s | 58.801us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 1.500m | 3.620ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 8.000s | 52.321us | 50 | 50 | 100.00 | ||
| spi_host_event | 19.167m | 111.907ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.567m | 10.001ms | 40 | 50 | 80.00 |
| V2 | speed | spi_host_speed | 11.567m | 10.001ms | 40 | 50 | 80.00 |
| V2 | chip_select_timing | spi_host_speed | 11.567m | 10.001ms | 40 | 50 | 80.00 |
| V2 | sw_reset | spi_host_sw_reset | 11.550m | 15.002ms | 34 | 50 | 68.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 8.000s | 190.267us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.567m | 10.001ms | 40 | 50 | 80.00 |
| V2 | full_cycle | spi_host_speed | 11.567m | 10.001ms | 40 | 50 | 80.00 |
| V2 | duplex | spi_host_smoke | 11.367m | 15.156ms | 38 | 50 | 76.00 |
| V2 | tx_rx_only | spi_host_smoke | 11.367m | 15.156ms | 38 | 50 | 76.00 |
| V2 | stress_all | spi_host_stress_all | 17.633m | 15.002ms | 39 | 50 | 78.00 |
| V2 | spien | spi_host_spien | 7.850m | 15.003ms | 43 | 50 | 86.00 |
| V2 | stall | spi_host_status_stall | 11.850m | 15.879ms | 33 | 50 | 66.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 13.233m | 200.000ms | 36 | 50 | 72.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 1.500m | 3.620ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 7.000s | 47.479us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 8.000s | 52.457us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 9.000s | 39.059us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 9.000s | 39.059us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 2.000s | 18.599us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 52.617us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 48.776us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 69.019us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 2.000s | 18.599us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 52.617us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 48.776us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 69.019us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 615 | 690 | 89.13 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 8.000s | 88.156us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 8.000s | 66.915us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 8.000s | 88.156us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 58.483m | 100.001ms | 1 | 10 | 10.00 | |
| TOTAL | 744 | 840 | 88.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.00 | 90.92 | 83.18 | 92.77 | 89.69 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 19 failures:
Test spi_host_spien has 4 failures.
0.spi_host_spien.112252552051073460351439611144408328722214710087585659105807934908150380040134
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 10000918126 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5659e954, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000918126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_spien.18262912791411028129757856703670051952263125110201924731544238628103676565042
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_spien/latest/run.log
UVM_FATAL @ 10007817414 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2f2c1454, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10007817414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_upper_range_clkdiv has 2 failures.
4.spi_host_upper_range_clkdiv.84785589177967598826992034136811783410530189769942141435377816107745175807922
Line 337, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002946888 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2e4ecc14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100002946888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_upper_range_clkdiv.20358796637067099467851335687113434031494301741137450753153065446262936751516
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004349315 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4a54a694, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100004349315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 4 failures.
5.spi_host_stress_all.83707735202347293336575907710988027371141150055172645442284358152197459964449
Line 348, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001768359 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc61acf54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001768359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_stress_all.25275529182992595903547561897393186946368427603645057359274360019602154650518
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001743240 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x511bf0d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001743240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_smoke has 6 failures.
9.spi_host_smoke.54853419895120360186956774223944352602529715209863298453343188479950142298643
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_smoke/latest/run.log
UVM_FATAL @ 15006287768 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7d277894, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15006287768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_host_smoke.114635436707031304575143239993320995545546219478204756656484982548493059572705
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_smoke/latest/run.log
UVM_FATAL @ 15004690755 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdbe18154, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15004690755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_speed has 3 failures.
19.spi_host_speed.84444955296528721702995836149898098781114229729422644164772118202692140852557
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_speed/latest/run.log
UVM_FATAL @ 10000718392 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x681dff54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000718392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_speed.10618461740055511732393470402635712076338562681904034235356120004068719299646
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_speed/latest/run.log
UVM_FATAL @ 10003965871 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4a804794, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003965871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 14 failures:
1.spi_host_upper_range_clkdiv.91241553262301962791016214679503915536679858453024333147956670937975853195372
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003925655 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x67e93d14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003925655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_upper_range_clkdiv.76324799595698460683799053196482703089592072417657663974424883374673733043430
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002489783 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x817c3494, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100002489783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
2.spi_host_smoke.95032382950952041879945735009843852654175983584495633549758257116126759632557
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_smoke/latest/run.log
UVM_FATAL @ 15011275316 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x69e85154, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15011275316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_smoke.24353741651003409684849250877720255879445378253797429630181980527663815458348
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_smoke/latest/run.log
UVM_FATAL @ 15002725518 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc5db2ed4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002725518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
13.spi_host_speed.84031017037692719572786573467186257303217204705459604411172716349480126614323
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_speed/latest/run.log
UVM_FATAL @ 10000934391 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa77be014, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000934391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.spi_host_speed.96740250570827150767649369250682084314455734230008171706676351080206925685983
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_speed/latest/run.log
UVM_FATAL @ 10001717864 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x62028ad4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001717864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
13.spi_host_stress_all.92062279558393953619731135181682043285556011892710880458801516282777251719112
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15000710406 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe5e5d854, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000710406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.spi_host_stress_all.27534708910221354206829092860902514401132203873636328320019245490949170452658
Line 346, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15002047391 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x74366714, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002047391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
23.spi_host_spien.68861422443079226769169572820261147092340958617990054407877028779097382685745
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_spien/latest/run.log
UVM_FATAL @ 15003369758 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6bf90454, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15003369758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 6 failures:
Test spi_host_sw_reset has 3 failures.
13.spi_host_sw_reset.62296225287060983463685116801177408944563895543301260544160453970584363443103
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10010499613 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe34d0154, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10010499613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.spi_host_sw_reset.3956548419595247646406839842211778160037257637369369253814292817580834694449
Line 364, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10034606340 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6c53ddd4, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10034606340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_smoke has 1 failures.
17.spi_host_smoke.62059588987400139225499765984695105478974042942346204858629913584475632801680
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_smoke/latest/run.log
UVM_FATAL @ 15155853747 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa6d6ecd4, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 15155853747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
17.spi_host_stress_all.30859148132162168623388164373153886754557980207466326377929731236325737162401
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10053551009 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8b647914, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10053551009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 1 failures.
45.spi_host_speed.30719578548824006464294725517384270764163353485581896337449746487755325252014
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_speed/latest/run.log
UVM_FATAL @ 10013580729 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa2673954, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10013580729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
16.spi_host_idlecsbactive.59678779080148975527247131863554466756853439917617255629787435333585217221832
Line 387, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_host_idlecsbactive.17408367538893972402445005802317337635969627392979545597247672035921328341319
Line 395, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 4 failures:
5.spi_host_idlecsbactive.98262713749902034333173534686991284411296674410512874964120422034139928809460
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15019710553 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x98e4614, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 15019710553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.spi_host_idlecsbactive.22468884256104701887679012657628116480040427381089009899316991465529066685840
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10015392632 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x58837e14, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10015392632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 3 failures:
10.spi_host_idlecsbactive.7570177509154374842333122749565514468699749005725547310702010958705501375494
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10016982958 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1ecb4d4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10016982958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_host_idlecsbactive.45195808638165507569738229511872323137976899988139287216806124654150421634643
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15009385749 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb6cb7754, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15009385749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 2 failures:
1.spi_host_stress_all.20145352701981804858144899612185808821335157142351786044460220922357540991505
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15010086125 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xaaf43fd4, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 15010086125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_stress_all.88241219169238920767201137804810390281616221632554616358583436388617685052843
Line 415, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22599466207 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x19f07d4, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 22599466207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
Test spi_host_upper_range_clkdiv has 1 failures.
2.spi_host_upper_range_clkdiv.31844186304068485249265052675900084929639058769702300733900129069286075575884
Line 325, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100006073528 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4491bd94, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 100006073528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_idlecsbactive has 1 failures.
38.spi_host_idlecsbactive.69767833575422644048869176317941265502780395039063268251256327440624926533974
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10009653189 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x120cd7d4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10009653189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
3.spi_host_sw_reset.33407101021512465924955964707429434921006585228324363133631554209694738366717
Line 334, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15004898029 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7ef93dd4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15004898029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.spi_host_sw_reset.23513996818067285538373719676902135876498320975801580899568373345196332942422
Line 348, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001509272 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xaaa45394, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10001509272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=81) has 2 failures:
11.spi_host_status_stall.54515996144231246609794882624889845092207197957905759286887163001463634379579
Line 907, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10418086398 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd8089254, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
UVM_INFO @ 10418086398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_host_status_stall.53082127670089231045619668758379267744089351499588641213065710130046457705001
Line 917, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10292233974 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf16b5e54, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
UVM_INFO @ 10292233974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 2 failures:
12.spi_host_sw_reset.20720038398883485763531162038454833261022166844200890869342744479123226643727
Line 326, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10029902108 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x91e911d4, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10029902108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_host_sw_reset.105373303170458685997552248194259934913511950558319670652964888395453015926905
Line 328, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10010243519 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5ee54714, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10010243519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 2 failures:
Test spi_host_speed has 1 failures.
15.spi_host_speed.84842783817103260592269750969632189935825849681265054433619935444976991748559
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_speed/latest/run.log
UVM_FATAL @ 10011541399 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x49731514, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10011541399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
48.spi_host_spien.92357174118322161901310893712709529859656386082489141412066320619533358950236
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_spien/latest/run.log
UVM_FATAL @ 10043566813 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x86fbc614, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10043566813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
15.spi_host_status_stall.50389170699614683733216207279634364678330543361888460028288550095478566332474
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10004324119 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf5343b54, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10004324119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.spi_host_status_stall.8756323794883001092975210423054410151445009437336230699411306746311423307074
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10005998750 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd4c7a594, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10005998750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:
17.spi_host_status_stall.10186071043343825702162797095620828815397429401165783643422561424098475169574
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_status_stall/latest/run.log
UVM_ERROR @ 1239176 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1239176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_host_status_stall.32442308512447865743328138478203375404241315416904114881842298445765507469737
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_status_stall/latest/run.log
UVM_ERROR @ 2900926 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2900926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
18.spi_host_sw_reset.104065168379594818940474850087390640725049595696953674389128053399699439016350
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10007302903 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfd8b4a94, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10007302903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_sw_reset.9144305239935154796700996354990058591924079527054642964499049210728118892707
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003172770 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x48d2e594, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10003172770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
31.spi_host_sw_reset.58183485668175067185397379700290856808905545427478377734830756912048412854730
Line 368, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10008581836 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7ca9f2d4, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10008581836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.spi_host_sw_reset.70102101966461667585984782295112835376928199917651683978580314764267850131086
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15001709818 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe1f8854, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 15001709818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
0.spi_host_upper_range_clkdiv.55436948458891097876129273323764266154030140719076809645998074789827126024956
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 190401505465 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbf909c54, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 190401505465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
0.spi_host_idlecsbactive.15451701662045778636720848779598555372065341534860846425188270900537753170377
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10005183394 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x30d8f654, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10005183394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
1.spi_host_smoke.10232057293865508640079368490586071196359043632265277882507153487128779512903
Line 415, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_smoke/latest/run.log
UVM_FATAL @ 15086248463 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x674514, Comparison=CompareOpEq, exp_data=0x1, call_count=27)
UVM_INFO @ 15086248463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
1.spi_host_sw_reset.110611526106306311256879886795877768531260092887366459143536238492857500208071
Line 434, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10031549581 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3ad03a94, Comparison=CompareOpEq, exp_data=0x0, call_count=30)
UVM_INFO @ 10031549581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
3.spi_host_upper_range_clkdiv.78835818228972465611008007162750215767550903697407438044602868627611882112353
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:164066ae-2a02-4358-b0c8-e626288c0a0a
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=78) has 1 failures:
3.spi_host_status_stall.99687544098690110943610032253463247643334655950310829542175186560968069990114
Line 909, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10650682350 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7e37ad54, Comparison=CompareOpEq, exp_data=0x1, call_count=78)
UVM_INFO @ 10650682350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
7.spi_host_upper_range_clkdiv.14755972239395180092702613454580215070203036379797719722984756231218205921902
Line 307, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005758109 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x6686e9d4, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 100005758109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
7.spi_host_status_stall.74867290622276107948835942413345344730838331294010631856506140357289316608541
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10004539356 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x475ec414, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10004539356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
12.spi_host_status_stall.38075956925353711086179397279189179069097167333596316837723159994887191738752
Line 421, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15879428020 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x77f13994, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 15879428020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
17.spi_host_sw_reset.18977688057931949101501869244141517252804366235284927043780756321359263203386
Line 308, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001969182 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x39518d54, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10001969182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=176) has 1 failures:
18.spi_host_status_stall.18025799363062330347378138609503635621938380555192566421632858942486938296672
Line 1044, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15135618312 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdc2d1a54, Comparison=CompareOpEq, exp_data=0x0, call_count=176)
UVM_INFO @ 15135618312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
23.spi_host_stress_all.96470897638212879778071254923452550126882943228344767820313350886586671748506
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15016016428 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5d46fd14, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 15016016428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
24.spi_host_status_stall.68391378737650120127003029161152494283416670997539673617194852941665819467603
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15034480155 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xdde5a5d4, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 15034480155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
28.spi_host_speed.81591593319697150186230568229687590175285504649542532902204643351220463084842
Line 379, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_speed/latest/run.log
UVM_FATAL @ 10066718906 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe307f254, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10066718906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
28.spi_host_status_stall.63167996802303251116614193571272296656771123344460811983076614949808096987479
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10036934812 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfccd5f94, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10036934812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
30.spi_host_smoke.41759789036123052860469622692265156188264528559802267993705355836459020990056
Line 1111, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_smoke/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=38) has 1 failures:
35.spi_host_spien.17482531999054264841149722355172546187016760071192878184293141262868246075505
Line 463, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_spien/latest/run.log
UVM_FATAL @ 10018232052 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x52da3994, Comparison=CompareOpEq, exp_data=0x1, call_count=38)
UVM_INFO @ 10018232052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 1 failures:
36.spi_host_status_stall.67731855718984717578841246911351123170045333812378344601329603829515109823026
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_status_stall/latest/run.log
UVM_ERROR @ 2836168 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 2836168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=163) has 1 failures:
38.spi_host_status_stall.97032911696042469702622533812093174273901736708063796749736910782850014697670
Line 988, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
UVM_FATAL @ 21615027932 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xad3cc954, Comparison=CompareOpEq, exp_data=0x0, call_count=163)
UVM_INFO @ 21615027932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=34) has 1 failures:
39.spi_host_sw_reset.84675406971482222926475884421117858449782748256251672017905413879724580348082
Line 444, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10112408272 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4c0b6094, Comparison=CompareOpEq, exp_data=0x0, call_count=34)
UVM_INFO @ 10112408272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
43.spi_host_sw_reset.42393517643082145028615849933645696872336560401657186184571549613250876887421
Line 451, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10025274387 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xca678f14, Comparison=CompareOpEq, exp_data=0x1, call_count=30)
UVM_INFO @ 10025274387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
43.spi_host_status_stall.107626675077933437732853123852761333207732509930069971686754780608920226229519
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003585641 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9b890dd4, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10003585641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
44.spi_host_status_stall.22834595441398040850188215936303011359671365862071545750778657879687082601943
Line 461, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10602372646 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa90df294, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
UVM_INFO @ 10602372646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=175) has 1 failures:
46.spi_host_status_stall.70124231093304306881323168926579637898392632489634931680111710175304808400928
Line 1030, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_status_stall/latest/run.log
UVM_FATAL @ 17193025370 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd554aad4, Comparison=CompareOpEq, exp_data=0x0, call_count=175)
UVM_INFO @ 17193025370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
49.spi_host_sw_reset.78124062256918703012940657877916112013556623501734736627971894677494141791064
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001325772 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x78c495d4, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10001325772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---