eca25c0ff8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 16.233m | 15.001ms | 36 | 50 | 72.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 7.000s | 20.565us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 12.000s | 53.205us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 8.000s | 131.750us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 7.000s | 23.770us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 8.000s | 109.997us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 12.000s | 53.205us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 7.000s | 23.770us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 189.474us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 3.000s | 39.452us | 5 | 5 | 100.00 |
| V1 | TOTAL | 101 | 115 | 87.83 | |||
| V2 | performance | spi_host_performance | 13.000s | 111.168us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.600m | 3.418ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 12.000s | 40.807us | 50 | 50 | 100.00 | ||
| spi_host_event | 7.817m | 11.460ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 7.350m | 10.002ms | 39 | 50 | 78.00 |
| V2 | speed | spi_host_speed | 7.350m | 10.002ms | 39 | 50 | 78.00 |
| V2 | chip_select_timing | spi_host_speed | 7.350m | 10.002ms | 39 | 50 | 78.00 |
| V2 | sw_reset | spi_host_sw_reset | 7.833m | 17.511ms | 41 | 50 | 82.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 12.000s | 198.714us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 7.350m | 10.002ms | 39 | 50 | 78.00 |
| V2 | full_cycle | spi_host_speed | 7.350m | 10.002ms | 39 | 50 | 78.00 |
| V2 | duplex | spi_host_smoke | 16.233m | 15.001ms | 36 | 50 | 72.00 |
| V2 | tx_rx_only | spi_host_smoke | 16.233m | 15.001ms | 36 | 50 | 72.00 |
| V2 | stress_all | spi_host_stress_all | 17.067m | 15.169ms | 41 | 50 | 82.00 |
| V2 | spien | spi_host_spien | 14.000m | 15.001ms | 42 | 50 | 84.00 |
| V2 | stall | spi_host_status_stall | 8.133m | 44.716ms | 35 | 50 | 70.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 12.900m | 200.000ms | 40 | 50 | 80.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.600m | 3.418ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 12.000s | 15.804us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 12.000s | 14.947us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 13.000s | 36.808us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 13.000s | 36.808us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 7.000s | 20.565us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 12.000s | 53.205us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 7.000s | 23.770us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 12.000s | 26.175us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 7.000s | 20.565us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 12.000s | 53.205us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 7.000s | 23.770us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 12.000s | 26.175us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 628 | 690 | 91.01 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 7.000s | 51.740us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 7.000s | 67.490us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 7.000s | 51.740us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 56.650m | 168.999ms | 1 | 10 | 10.00 | |
| TOTAL | 755 | 840 | 89.88 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.92 | 95.70 | 100.00 | 95.07 | 90.46 |
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 25 failures:
Test spi_host_spien has 6 failures.
0.spi_host_spien.38566219315872826885253293593674428771220301502566971689235412926312481820757
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 15001386289 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x87a244d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001386289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_spien.25853535214912822376978374942149083959081406017715415506084336359789797319763
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_spien/latest/run.log
UVM_FATAL @ 10004322005 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe83a3b14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004322005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_speed has 6 failures.
3.spi_host_speed.110912733431791435159417142243578595366763364098379095008766708039909770897222
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_speed/latest/run.log
UVM_FATAL @ 10000871846 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x585e61d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000871846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_host_speed.32688632341148954700244067805734739600912595126919331596251119483537843549276
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_speed/latest/run.log
UVM_FATAL @ 10004238528 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xda071494, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004238528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_stress_all has 2 failures.
7.spi_host_stress_all.57355716433244758715837184132188041638704414327715104682738517659930688274280
Line 340, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10001889457 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe0b57e94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001889457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.spi_host_stress_all.5365125705851747793131308664885542034721644311047575983311687035701865589531
Line 326, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15008338098 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x363af814, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15008338098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_upper_range_clkdiv has 2 failures.
8.spi_host_upper_range_clkdiv.10827215013048584065314521576361260007718773123940680688968483468134994497265
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003660478 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa71ff1d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003660478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_host_upper_range_clkdiv.39174898310772329174157005409295488065555379632847583351246357182698505135785
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100001932827 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6ed85454, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100001932827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 9 failures.
18.spi_host_smoke.106478158183951094069556300177695752966115424203541032611836996552657323546406
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000887856 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2ddc3654, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000887856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.spi_host_smoke.91572495684083311598308534688677048236044762700786084384131153046792103312290
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000833403 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x43621a54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000833403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 11 failures:
Test spi_host_upper_range_clkdiv has 2 failures.
1.spi_host_upper_range_clkdiv.28190354317402840340026806510813739294080856320737766059680707200164528388733
Line 315, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003129031 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x21c67114, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003129031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_host_upper_range_clkdiv.109957995975582832905770670499941029315858956836111384192206344095507034754454
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100007594419 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6288a054, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100007594419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 1 failures.
2.spi_host_spien.72479406602040723412216021590875888803838908941689875255878622585681260663526
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_spien/latest/run.log
UVM_FATAL @ 15001140544 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe91d3054, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001140544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 4 failures.
12.spi_host_smoke.10292142566936622393284254516169255428640313190299835136838051511272842801534
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_smoke/latest/run.log
UVM_FATAL @ 15003804138 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x86081e14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15003804138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_host_smoke.40877668453906798575926776660244654898944050831279033071616283932450335812113
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_smoke/latest/run.log
UVM_FATAL @ 15010006625 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6eef0e54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15010006625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test spi_host_stress_all has 3 failures.
18.spi_host_stress_all.24862977106866101492618337837988865025898842090978315961875588031009608371517
Line 340, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10001725542 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xef291bd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001725542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_host_stress_all.43297090382305786943022261806347279254184658346606023090048787869880858822695
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10001484033 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x292ec754, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001484033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_speed has 1 failures.
46.spi_host_speed.81962655082819752065634811032913828476150229040152387745538960230096703970248
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_speed/latest/run.log
UVM_FATAL @ 10001742755 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xad775fd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001742755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 5 failures:
3.spi_host_idlecsbactive.19101684167807813130342039295648275323217602144740810466940665849983593043580
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15007962542 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9c805b14, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 15007962542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_host_idlecsbactive.1795837904327150708879038676406722645281449178752795261543217666205196597532
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002345282 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5795f214, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10002345282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 4 failures:
5.spi_host_sw_reset.45941480693751648825548854481026029948148520362284167933853401392192660365193
Line 326, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001652038 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3ad16714, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10001652038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_host_sw_reset.35140342019358693020139497953423830153281074000598473157143409057052619122080
Line 326, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001258405 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x18807154, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10001258405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 3 failures:
9.spi_host_status_stall.28119700792790967030248577155004940435298210466452588880690711677064856414229
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10004075223 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb9bb0214, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10004075223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.spi_host_status_stall.71034889902978102579023078242427109274404542132215616968205237262135228646868
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10001591947 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcefc6154, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10001591947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 3 failures:
22.spi_host_status_stall.111577501222745653987567890447862713084485987685797451039641774761813481766952
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log
UVM_ERROR @ 6018539 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 6018539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_host_status_stall.66539976832301122617553832177998085535190575404489367705026524491449149691649
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
UVM_ERROR @ 6672095 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 6672095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
2.spi_host_status_stall.67403204841656466930024021604093634718329737654670756009300988769944732536816
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003478221 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9331fed4, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10003478221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.spi_host_status_stall.28934064686296626251541209804813569893237261514009613570483657056824783136782
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15020270802 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7acc4c14, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 15020270802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
5.spi_host_upper_range_clkdiv.71175660206728836880170869119296245343168627003004173898263232879018104158712
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:d6708fec-03e2-4b8d-9fe1-b74ba0b226ae
7.spi_host_upper_range_clkdiv.68050842946861378331248955961180652729816437843672906818824063611447125779207
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:806ab1c1-cc21-4570-aad3-554e9af398f7
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 2 failures:
Test spi_host_spien has 1 failures.
10.spi_host_spien.50940542913456798483370702264666766775997463694253380202723591754031012224115
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_spien/latest/run.log
UVM_FATAL @ 10014970425 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3c83b294, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10014970425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
19.spi_host_status_stall.30277984616595037363854240300307653619928160720190488528366552489150143411267
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10029962014 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5db5d354, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10029962014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
34.spi_host_idlecsbactive.43956726310999542203804974239252178729726636259145204882865511788307456237933
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10003099453 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x571b0d54, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10003099453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.spi_host_idlecsbactive.109459771721540831137752222852282505292986697439769346005653470688793022913857
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15008398704 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe9337894, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15008398704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
36.spi_host_idlecsbactive.114938729292563045466982849818144748941719672433440402571470374270553348666608
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.spi_host_idlecsbactive.165717916718339236479715434020999548770315989258316595584239217687151386231
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=33) has 2 failures:
41.spi_host_speed.111858068691917386242026592813915686100520489781892199085258677971906438168603
Line 427, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_speed/latest/run.log
UVM_FATAL @ 10165836075 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd11fd014, Comparison=CompareOpEq, exp_data=0x1, call_count=33)
UVM_INFO @ 10165836075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.spi_host_speed.23828779047070646451053733026754116107665894602776207467465415813560160522801
Line 411, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_speed/latest/run.log
UVM_FATAL @ 10229723371 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfca74f54, Comparison=CompareOpEq, exp_data=0x1, call_count=33)
UVM_INFO @ 10229723371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:367) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:
41.spi_host_status_stall.72796293317865072666380028924509389165682976408843465220353812265604403985588
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
UVM_ERROR @ 3720061 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3720061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.spi_host_status_stall.99377971988667056287676774584206661868195334388042149933285009526105069959296
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_status_stall/latest/run.log
UVM_ERROR @ 6174685 ps: (cip_base_vseq.sv:367) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6174685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
0.spi_host_upper_range_clkdiv.99178354592477026747570631064150647649810518800272317995290441473964502259191
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 176957943836 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x349d8354, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
UVM_INFO @ 176957943836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
2.spi_host_sw_reset.100022127841803968325347705564932025502338933220535118833603622429168374773521
Line 320, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10011808905 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc927a54, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10011808905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
3.spi_host_upper_range_clkdiv.44153489956988871363815833380018449802431845529925332003011705963379380775940
Line 355, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 168999354830 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x2dcd4254, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 168999354830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
4.spi_host_upper_range_clkdiv.60550510010092414292382444326994078884997053920791967241506700795482115857333
Line 319, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003516867 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc3b5b014, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 100003516867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
4.spi_host_sw_reset.51754313362065353925990822300617592319173310674404076175896407798741824760166
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001749375 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe99ff914, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10001749375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
6.spi_host_sw_reset.91060096223393012175249934433250999286886436111511133682223558620877043710670
Line 368, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10006060454 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x712a20d4, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10006060454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
9.spi_host_speed.30544163643000178024686132397197071564896564999909104955009279420894455976866
Line 387, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_speed/latest/run.log
UVM_FATAL @ 10020829736 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x306d3214, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
UVM_INFO @ 10020829736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=89) has 1 failures:
12.spi_host_status_stall.14008927262965811135882282579600667116686059365109290013926771162572830930736
Line 951, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10281697814 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9e817f14, Comparison=CompareOpEq, exp_data=0x1, call_count=89)
UVM_INFO @ 10281697814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
12.spi_host_stress_all.26580441964006980162477892457671727601458980102522080337080510380875393777209
Line 451, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_stress_all/latest/run.log
UVM_FATAL @ 17209256358 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc824b414, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 17209256358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
13.spi_host_status_stall.101133365568486613526474871914097613474083679854194237655525995896518066188149
Line 387, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10155406693 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf5e8c54, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10155406693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
18.spi_host_idlecsbactive.69485702905981978135914929312245433010743073753205129030716619474018177554657
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002388318 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1d33914, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10002388318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
22.spi_host_stress_all.32953457749955868836286999685489060004363656427775414773250946541964787932426
Line 410, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10054048476 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x77c89114, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10054048476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
23.spi_host_sw_reset.66265952411324523805771652527465475858411166628200956698194311857771288652018
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002216780 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9b92c094, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10002216780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
25.spi_host_speed.88046068559614941074018375277185050039483774411251882035836602102071596768037
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_speed/latest/run.log
UVM_FATAL @ 10006074082 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4b92a314, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10006074082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=83) has 1 failures:
27.spi_host_status_stall.39610174124642398006188052247062384410206167696395654424229444672671814270745
Line 925, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10469555053 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x55d20814, Comparison=CompareOpEq, exp_data=0x1, call_count=83)
UVM_INFO @ 10469555053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
30.spi_host_smoke.109253202005683384558558513060337953569714835016476135016065114153990263285622
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_smoke/latest/run.log
UVM_FATAL @ 15328619793 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7335994, Comparison=CompareOpEq, exp_data=0x1, call_count=25)
UVM_INFO @ 15328619793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
37.spi_host_sw_reset.21850939037375518299388253608615014036655175038743809317849186431126979339797
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10007574537 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5f4e1b94, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10007574537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
38.spi_host_stress_all.73213959903799643177715688501372864330850643329410902065944206278820183248751
Line 430, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15168581073 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe541254, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
UVM_INFO @ 15168581073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
40.spi_host_stress_all.88764377941554291030656431973265831321927740099170882913668268717032610904307
Line 412, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22728230952 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x173d514, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 22728230952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=88) has 1 failures:
48.spi_host_status_stall.91422876601082095864701142699620682736176481827584907167335155234039071647775
Line 959, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10223446984 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x7c6e654, Comparison=CompareOpEq, exp_data=0x1, call_count=88)
UVM_INFO @ 10223446984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---