39f3866b56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 17.017m | 15.001ms | 34 | 50 | 68.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 31.094us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 3.000s | 17.681us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 600.165us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 62.248us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 3.000s | 38.906us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 3.000s | 17.681us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 62.248us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 16.715us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 2.000s | 60.469us | 5 | 5 | 100.00 |
| V1 | TOTAL | 99 | 115 | 86.09 | |||
| V2 | performance | spi_host_performance | 18.000s | 34.672us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 1.117m | 7.091ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 7.000s | 23.594us | 50 | 50 | 100.00 | ||
| spi_host_event | 7.850m | 46.556ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.217m | 10.001ms | 41 | 50 | 82.00 |
| V2 | speed | spi_host_speed | 11.217m | 10.001ms | 41 | 50 | 82.00 |
| V2 | chip_select_timing | spi_host_speed | 11.217m | 10.001ms | 41 | 50 | 82.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.283m | 15.002ms | 39 | 50 | 78.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 9.000s | 492.582us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.217m | 10.001ms | 41 | 50 | 82.00 |
| V2 | full_cycle | spi_host_speed | 11.217m | 10.001ms | 41 | 50 | 82.00 |
| V2 | duplex | spi_host_smoke | 17.017m | 15.001ms | 34 | 50 | 68.00 |
| V2 | tx_rx_only | spi_host_smoke | 17.017m | 15.001ms | 34 | 50 | 68.00 |
| V2 | stress_all | spi_host_stress_all | 16.800m | 15.001ms | 41 | 50 | 82.00 |
| V2 | spien | spi_host_spien | 11.650m | 15.083ms | 36 | 50 | 72.00 |
| V2 | stall | spi_host_status_stall | 7.100m | 19.636ms | 36 | 50 | 72.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 8.233m | 200.000ms | 34 | 50 | 68.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 1.117m | 7.091ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 8.000s | 18.968us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 3.000s | 52.269us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 163.663us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 163.663us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 31.094us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 17.681us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 62.248us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 26.414us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 31.094us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 3.000s | 17.681us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 62.248us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 3.000s | 26.414us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 617 | 690 | 89.42 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 235.034us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 7.000s | 65.622us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 235.034us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 59.650m | 100.001ms | 0 | 10 | 0.00 | |
| TOTAL | 741 | 840 | 88.21 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.92 | 95.70 | 100.00 | 95.07 | 90.46 |
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 27 failures:
Test spi_host_upper_range_clkdiv has 3 failures.
2.spi_host_upper_range_clkdiv.80284509778705148277583276431894018245492532188887587722898861692977619663407
Line 315, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003474704 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3b8dfb54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003474704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_upper_range_clkdiv.26032630632959404433503592907638542211944968993520394519475989588120734772846
Line 325, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100000752707 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x50d1b014, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100000752707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_stress_all has 2 failures.
2.spi_host_stress_all.109679001853893211387215986485315510915325417832718049929775472522869599345732
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10001508757 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc8a2b1d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001508757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.spi_host_stress_all.74447334554589712653707136038423347895612178289062878108341980624530451598975
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001065201 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc665d954, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001065201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 6 failures.
3.spi_host_smoke.40616786239427145093255104923873342215174211478213905564147134556866743300645
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000719870 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3163bc54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000719870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_smoke.994196798799473780645523872884537151626684273901808749537511309449747493555
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_smoke/latest/run.log
UVM_FATAL @ 15003862618 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa3b88cd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15003862618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_spien has 8 failures.
5.spi_host_spien.46609989767267907956844402923963762223006240976297478054863884477687739410623
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_spien/latest/run.log
UVM_FATAL @ 10001713079 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x413a9454, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001713079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.spi_host_spien.10559119792613915285702798000560388651910434314608727629421166992128939017710
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_spien/latest/run.log
UVM_FATAL @ 10001234948 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xccef2854, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001234948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test spi_host_speed has 8 failures.
6.spi_host_speed.21264058444026600059385533194124768038047591850488608604455410661005571946253
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/latest/run.log
UVM_FATAL @ 10003431530 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4e561a14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003431530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.spi_host_speed.35154967001048837929570353175653234953283769094250652182742469524750102548551
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_speed/latest/run.log
UVM_FATAL @ 10000794275 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc25f5214, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000794275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 13 failures:
Test spi_host_stress_all has 2 failures.
4.spi_host_stress_all.103754141246428805323171619573896486067298578203635653357687299042741707212443
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10003818900 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x21a6f7d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003818900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_stress_all.107616971859452616316896367550954302406220447919163581865250006426410585623185
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15000848729 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xcd018914, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000848729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_upper_range_clkdiv has 1 failures.
5.spi_host_upper_range_clkdiv.27274752330910085238811681677498584904976220124421446599347601025355633713830
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004080363 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x596ee714, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100004080363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_smoke has 6 failures.
7.spi_host_smoke.71925670383138242115046223301519174606921776811136508189422451667021216415301
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_smoke/latest/run.log
UVM_FATAL @ 15003128023 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xae338e14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15003128023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_smoke.54296013665841509622745802638355968393644851032617768446177516161378921961864
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_smoke/latest/run.log
UVM_FATAL @ 15002075672 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x671ec654, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002075672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_spien has 4 failures.
9.spi_host_spien.105920791170061961103852052103694780381059739541240426100308225237358891116378
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_spien/latest/run.log
UVM_FATAL @ 10001177680 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5fb3ac14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001177680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.spi_host_spien.95894660944056398803870215451775292503117471363219237301776255425827644239629
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_spien/latest/run.log
UVM_FATAL @ 10001030875 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3eb6bfd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001030875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 6 failures:
0.spi_host_idlecsbactive.90350296538554366858962431845116147334003726342373773898605236575988222137337
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002684158 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3d833d54, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10002684158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_idlecsbactive.41722540623619496805642752433311046504199017905916380078928247671989253984338
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10010370541 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7a597414, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10010370541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 5 failures:
6.spi_host_idlecsbactive.67665198922563777433708317088815441885148080270112518786539939221164441690338
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10006994106 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x64e95594, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10006994106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_host_idlecsbactive.20448043520408145920816935854113356915676213639888111950659268824203938712211
Line 331, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002125165 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf442b14, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10002125165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 4 failures:
1.spi_host_status_stall.9468958729445959666608372424803579454935273403041360764970581155999924652426
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10046235694 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xabde0d94, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10046235694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_host_status_stall.65283169268023449039025013478842827439706559430128518935979830620211833686358
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10007629622 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2b11aed4, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10007629622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
1.spi_host_upper_range_clkdiv.96752735220359832216332787120224835625974086316260549991860701091156770763098
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:88403776-d886-4856-a623-be8e2c0ef81b
4.spi_host_upper_range_clkdiv.110117573075049798172908489055271488435319007776430560944201733718889297472504
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:0f634a45-f8e7-46e7-9128-47f9caa15e31
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 3 failures:
15.spi_host_sw_reset.30411724762505390598811457716544405265853030630632797832828305083494314197964
Line 338, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001512320 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x18ac8614, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10001512320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.spi_host_sw_reset.58225400161675656576408565592981824839926758105228532353390404202627299321559
Line 322, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15002182065 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbae12e54, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 15002182065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
1.spi_host_sw_reset.114988619477992403986879513413377286473100636323852085346712031664420988214401
Line 330, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003747243 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa1f89914, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10003747243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_sw_reset.45284026791756574645747495403259260986271770454803809347667506922425015035637
Line 340, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15003834874 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1e468ed4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15003834874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
3.spi_host_idlecsbactive.88353650130950623969621670540913459203241565453050940340980374763959297666598
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002333028 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xa7a14c14, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10002333028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.spi_host_idlecsbactive.96303526293445423479981681116133906882669436576250350555872278605362620031064
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10018356926 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9ecb2c14, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10018356926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:364) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:
24.spi_host_status_stall.90500948694208476910802365452336391181980936490547104294047713184891857062443
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_status_stall/latest/run.log
UVM_ERROR @ 17267589 ps: (cip_base_vseq.sv:364) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 17267589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.spi_host_status_stall.77922464748977515065590652303074842678953046453949540087392825938059286480248
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_status_stall/latest/run.log
UVM_ERROR @ 2193165 ps: (cip_base_vseq.sv:364) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2193165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
25.spi_host_status_stall.58868050680156863288307385737368557696475225283537751305633851441857066315563
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15013468999 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4d7a66d4, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 15013468999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_status_stall.90241280405492412082127687865820005239072281527118528645007966746804865334465
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10006885338 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3b058854, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10006885338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
29.spi_host_sw_reset.91706851636502193702034644097703811596362727023801323670227559459076081919056
Line 358, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10004235287 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x31425c14, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10004235287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.spi_host_sw_reset.61961815384247648815788776182318294158333666825498600349340839309583702902777
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10015958920 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xcecf214, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10015958920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=81) has 2 failures:
31.spi_host_status_stall.79378912787311583295752266271601482348046771753930465366068433481574990518282
Line 919, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10246850975 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5c3c0fd4, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
UVM_INFO @ 10246850975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.spi_host_status_stall.62280020989715239437535285651109388528058045774467164340794561743404658738319
Line 923, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_status_stall/latest/run.log
UVM_FATAL @ 11098398545 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x13cb3094, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
UVM_INFO @ 11098398545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=32) has 2 failures:
Test spi_host_stress_all has 1 failures.
33.spi_host_stress_all.95384399475894966779092217962525760403573824039347880517826381094683438706957
Line 498, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15085378578 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5558c154, Comparison=CompareOpEq, exp_data=0x0, call_count=32)
UVM_INFO @ 15085378578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 1 failures.
40.spi_host_sw_reset.66892091136498111643610801017958973285222188950380978792292763090613686999968
Line 427, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10045435563 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x95825d4, Comparison=CompareOpEq, exp_data=0x0, call_count=32)
UVM_INFO @ 10045435563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
0.spi_host_upper_range_clkdiv.39297388682830726816493603978975339917009231522745846826159701347273439100255
Line 371, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 194654646591 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbd6f3bd4, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 194654646591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
3.spi_host_upper_range_clkdiv.85161818973660935079100263813949774033393724838981499147498733181722942441256
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
4.spi_host_status_stall.18255541818421469115982451365492314813005991969187785264621161293371735317938
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10001838922 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x58b7e194, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10001838922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=33) has 1 failures:
6.spi_host_sw_reset.4975473955174387570992975608385448892024501642681258028299605566163823615148
Line 465, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10027720664 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2767f914, Comparison=CompareOpEq, exp_data=0x1, call_count=33)
UVM_INFO @ 10027720664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
8.spi_host_upper_range_clkdiv.12786680384131402453717468242285021836071576408863340690155044717469012490535
Line 303, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002256073 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x776f3cd4, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 100002256073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
9.spi_host_smoke.104336579844073447911154539526115981378201237602938281505696120235666077722444
Line 407, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_smoke/latest/run.log
UVM_FATAL @ 15563896730 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x11bf614, Comparison=CompareOpEq, exp_data=0x1, call_count=27)
UVM_INFO @ 15563896730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
11.spi_host_sw_reset.5357227870750546779688260982563978615965352942759585810601882637041785052772
Line 346, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10004161231 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8f048dd4, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10004161231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 1 failures:
12.spi_host_status_stall.35642223248552310278118874526182435498557066624843380704294570867813622612389
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log
UVM_ERROR @ 13668534 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 13668534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
15.spi_host_smoke.92601664354154609092551044805982287540716618970000911193544632179707260637853
Line 367, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_smoke/latest/run.log
UVM_FATAL @ 15718909122 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6dddf394, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 15718909122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=51) has 1 failures:
18.spi_host_speed.1166245228842756059496758718581842232291946026125214166165462153542363089642
Line 467, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_speed/latest/run.log
UVM_FATAL @ 10248093814 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6e807f14, Comparison=CompareOpEq, exp_data=0x1, call_count=51)
UVM_INFO @ 10248093814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
19.spi_host_stress_all.13575855412518166330703788163549199865492090612028665322242185025293638485305
Line 405, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/19.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22513924933 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x16a5ed14, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 22513924933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
25.spi_host_stress_all.35926528324916825938729364080634842645374611301806547863939205612447242106068
Line 411, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15038188082 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x43bfb14, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 15038188082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
27.spi_host_stress_all.83300451943673876811732878222833439968321970183604967759818007278249669083269
Line 425, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15380193888 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8bba5314, Comparison=CompareOpEq, exp_data=0x1, call_count=30)
UVM_INFO @ 15380193888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
27.spi_host_spien.108463532909465606066119117956474977607178834300885918401864432658206775540389
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_spien/latest/run.log
UVM_FATAL @ 15083321045 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa4934e54, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 15083321045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=32) has 1 failures:
28.spi_host_stress_all.62155285815962776630319150241920241405753277457065990555916372002377224943827
Line 474, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10070371267 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7074be14, Comparison=CompareOpEq, exp_data=0x0, call_count=32)
UVM_INFO @ 10070371267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
30.spi_host_sw_reset.56819499570275818202052237459698622862691798113127836475955764167426557924596
Line 395, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10043289574 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf66fc3d4, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
UVM_INFO @ 10043289574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=85) has 1 failures:
33.spi_host_status_stall.36214592721024334837415260241851493073556189065019695224356788749406553886503
Line 941, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10771603779 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xeadd47d4, Comparison=CompareOpEq, exp_data=0x1, call_count=85)
UVM_INFO @ 10771603779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
34.spi_host_idlecsbactive.61375751288473434443206309318898757837315496367740055184489073067807662569577
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15003426381 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe4d82c54, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15003426381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=38) has 1 failures:
36.spi_host_smoke.63042899335775188953246487831399383738076085022381758345767956426881152189319
Line 441, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_smoke/latest/run.log
UVM_FATAL @ 16032337538 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x46e93ad4, Comparison=CompareOpEq, exp_data=0x1, call_count=38)
UVM_INFO @ 16032337538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
39.spi_host_smoke.109471033531448488910708895127545488801137516120941302917412199876920716645499
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_smoke/latest/run.log
UVM_FATAL @ 15659528380 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2aed3f14, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 15659528380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
39.spi_host_idlecsbactive.61034025579158656953001333162887228516772927139525540814056470757090534027364
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002570978 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc09dd0d4, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10002570978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
41.spi_host_idlecsbactive.17397441207951446190972417131932277343514619884581528973883398862995588562378
Line 387, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
43.spi_host_status_stall.56694398949240595372443128689679940075048509216087589828798295184858585884343
Line 415, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10075717463 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x526c79d4, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10075717463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
44.spi_host_spien.92658595121946286761104202182077678710456449457893981685873567944093907349343
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_spien/latest/run.log
UVM_FATAL @ 10034636704 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe652d114, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10034636704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---