fdfa12db04| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 16.900m | 15.001ms | 36 | 50 | 72.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 8.000s | 47.722us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 12.000s | 42.709us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 20.000s | 629.543us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 2.000s | 70.596us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 8.000s | 186.293us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 12.000s | 42.709us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 2.000s | 70.596us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 15.714us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 7.000s | 51.896us | 5 | 5 | 100.00 |
| V1 | TOTAL | 101 | 115 | 87.83 | |||
| V2 | performance | spi_host_performance | 8.000s | 33.374us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 2.967m | 15.198ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 15.000s | 17.693us | 50 | 50 | 100.00 | ||
| spi_host_event | 18.550m | 100.855ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.417m | 10.001ms | 38 | 50 | 76.00 |
| V2 | speed | spi_host_speed | 11.417m | 10.001ms | 38 | 50 | 76.00 |
| V2 | chip_select_timing | spi_host_speed | 11.417m | 10.001ms | 38 | 50 | 76.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.283m | 15.069ms | 42 | 50 | 84.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 16.000s | 885.500us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.417m | 10.001ms | 38 | 50 | 76.00 |
| V2 | full_cycle | spi_host_speed | 11.417m | 10.001ms | 38 | 50 | 76.00 |
| V2 | duplex | spi_host_smoke | 16.900m | 15.001ms | 36 | 50 | 72.00 |
| V2 | tx_rx_only | spi_host_smoke | 16.900m | 15.001ms | 36 | 50 | 72.00 |
| V2 | stress_all | spi_host_stress_all | 15.000m | 22.528ms | 43 | 50 | 86.00 |
| V2 | spien | spi_host_spien | 7.483m | 10.002ms | 42 | 50 | 84.00 |
| V2 | stall | spi_host_status_stall | 7.883m | 10.267ms | 32 | 50 | 64.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 11.200m | 15.002ms | 35 | 50 | 70.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 2.967m | 15.198ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 9.000s | 26.812us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 12.000s | 39.866us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 14.000s | 64.906us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 14.000s | 64.906us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 8.000s | 47.722us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 12.000s | 42.709us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 2.000s | 70.596us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 8.000s | 61.435us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 8.000s | 47.722us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 12.000s | 42.709us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 2.000s | 70.596us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 8.000s | 61.435us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 622 | 690 | 90.14 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 13.000s | 153.259us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 2.000s | 397.102us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 13.000s | 153.259us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 55.833m | 184.656ms | 1 | 10 | 10.00 | |
| TOTAL | 749 | 840 | 89.17 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.01 | 90.92 | 83.18 | 92.77 | 89.77 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 24 failures:
0.spi_host_speed.44373787407004251828529238618803355868853041856127149667211479552554113514057
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log
UVM_FATAL @ 10000747421 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdadcb214, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000747421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.spi_host_speed.98332995275634926301529085815219626019623329922715325426229679490346332481996
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_speed/latest/run.log
UVM_FATAL @ 10001179713 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa1bf1dd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001179713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
2.spi_host_upper_range_clkdiv.8134853394232574164260415829805253486328075657037033352063975842440373360933
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100013691478 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8916f554, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100013691478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_upper_range_clkdiv.106584918001907047672867670402271871261111035394418596384951544064769409520345
Line 307, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003716414 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8dbbd014, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003716414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
3.spi_host_smoke.54349825213190310085954492987256451883814409988571287422125316377500772990875
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_smoke/latest/run.log
UVM_FATAL @ 15002143576 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe17649d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002143576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_smoke.5470683217653769258000906697367681347726502829522781366532279044104140340378
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_smoke/latest/run.log
UVM_FATAL @ 15006527571 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa7548c94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15006527571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
8.spi_host_stress_all.91519056693505531382948055872507785198585817649699943704052709359132840278393
Line 360, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10001953021 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe9fcb854, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001953021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.spi_host_stress_all.111843693619935417614874360080302831982295652347256767169440185572849109073700
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15007459327 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc297d354, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15007459327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
22.spi_host_spien.89685228057766679023174454095704957818318145798054985549652419990130282504540
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/22.spi_host_spien/latest/run.log
UVM_FATAL @ 10000820500 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7edcfed4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000820500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_spien.87747778428892279331750230311679989168438246408306265290304732663266217219069
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_spien/latest/run.log
UVM_FATAL @ 10000906303 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf083b014, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000906303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 14 failures:
Test spi_host_smoke has 8 failures.
0.spi_host_smoke.114813739664099898942773136853028816329484398390658816011284259248155334512234
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000784624 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xff514b54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000784624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_smoke.7004256442622919753634516326112303410394623251374457519802709204834370510330
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001498265 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8b57c414, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001498265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test spi_host_upper_range_clkdiv has 1 failures.
5.spi_host_upper_range_clkdiv.11078883063653469465992136789887097626068071135171009358277752507200981070300
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100011997381 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2e4c2a54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100011997381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 2 failures.
7.spi_host_spien.106300120922243961250813360829966760703200605549235875749941410204520627420596
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_spien/latest/run.log
UVM_FATAL @ 15002388267 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc4a40d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15002388267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_spien.7843072526630981577075868212753624154696095383697977963132970117440557826240
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_spien/latest/run.log
UVM_FATAL @ 10002218483 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x86411d54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10002218483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_speed has 2 failures.
17.spi_host_speed.68189473300529399703073559195033033547597412438968739938617819012207997071470
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_speed/latest/run.log
UVM_FATAL @ 10000796042 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xde1a3154, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000796042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_host_speed.26345936807563151507166502422623941499939859798817951198358929296222917161372
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_speed/latest/run.log
UVM_FATAL @ 10001842857 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbe5c05d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001842857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_stress_all has 1 failures.
34.spi_host_stress_all.3286092520953129140526628066726251575365987302333503356769742765171099968855
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15009794019 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc20da694, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15009794019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 7 failures:
11.spi_host_idlecsbactive.97852711661985670385710384419956213291777574443251076623387435707404746666879
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10015046426 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x171b4154, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10015046426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.spi_host_idlecsbactive.17719641591875761696071906917290552108576955338502870249680266363373251571301
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10008600012 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xb6a148d4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10008600012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 4 failures:
8.spi_host_status_stall.110707007498460238858628384650734603986940601940322553818688224314742450701489
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_status_stall/latest/run.log
UVM_ERROR @ 5935548 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 5935548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.spi_host_status_stall.66478295948561691795517882875959615960864321386859999468750584868977187489452
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_status_stall/latest/run.log
UVM_ERROR @ 71114402 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 71114402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
0.spi_host_upper_range_clkdiv.17416234781269261069640779237989070862339414937683749823258267162848908236671
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:13a9bd08-7835-411d-a477-df4bdfb50948
3.spi_host_upper_range_clkdiv.50627123172515513038625253409221667141338201261030610555976767133506642443694
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:7a5326ab-664c-4ead-97de-ec3abb35529b
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
1.spi_host_idlecsbactive.31294812518015194097390717517731420375103980613767488987139605559216994187660
Line 391, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_idlecsbactive.30813875326773844009587138963007659315997788460580914057944092771127452601236
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 3 failures:
12.spi_host_idlecsbactive.47022559180594760169424946149364789251563921479097521162337381089386153070536
Line 335, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002411025 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x73afa094, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10002411025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.spi_host_idlecsbactive.25602924784530060390644822505458747311027188226204682677405511396020790724273
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/26.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 15002315593 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7cdd17d4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 15002315593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 2 failures:
Test spi_host_smoke has 1 failures.
10.spi_host_smoke.108068141930487827126160548685663887381252763959022454245599063430092469522507
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_smoke/latest/run.log
UVM_FATAL @ 16787950918 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8a7ec9d4, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 16787950918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_status_stall has 1 failures.
39.spi_host_status_stall.100503951303479171547197369000982364530200056965480590246806716431319313544016
Line 385, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_status_stall/latest/run.log
UVM_FATAL @ 18490217854 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf295114, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 18490217854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
12.spi_host_status_stall.62217697586853038237514302605436878889622318971886248578701065223476520885808
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10007074704 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xbdfc8a94, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10007074704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.spi_host_status_stall.1188292442046192244254766840884100512569009601355823232423357762491118483403
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10006806797 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xecb48494, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10006806797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
14.spi_host_status_stall.39733238748545819234523713538482934008334636185769982261821460129571747596808
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10003569031 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x17aeba94, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10003569031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.spi_host_status_stall.80887983569179986799026460254337173459287135335046631994327931179993623153893
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15006794552 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x12288c94, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 15006794552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
41.spi_host_sw_reset.52710529512703450923020023181444441216044239850834843486154774851758480480220
Line 340, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/41.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10004179172 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd2487394, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10004179172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.spi_host_sw_reset.112105791859541983883243655822069947655167573687273106407721419959390154544677
Line 340, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10007147162 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8157a114, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10007147162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
1.spi_host_status_stall.93117037702600245124491172006571708479656129083898674153714000007207386798588
Line 381, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10013523914 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe57d8cd4, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10013523914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=41) has 1 failures:
5.spi_host_stress_all.114212589395727148498649108613144856179931641895285732959182108138148434301643
Line 454, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10052784431 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x75f33094, Comparison=CompareOpEq, exp_data=0x1, call_count=41)
UVM_INFO @ 10052784431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=42) has 1 failures:
6.spi_host_speed.76568330727337059262106995795842146295970037592495083125820639326295545789520
Line 465, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_speed/latest/run.log
UVM_FATAL @ 10540562856 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x45525054, Comparison=CompareOpEq, exp_data=0x1, call_count=42)
UVM_INFO @ 10540562856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
7.spi_host_upper_range_clkdiv.880576380629193477885149285531412502571534698071356444445258577109102047170
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 184655963804 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x62ab9654, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 184655963804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:364) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:
7.spi_host_status_stall.74781402046001474057369079713335050889553604895281364710802019672596761245455
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_status_stall/latest/run.log
UVM_ERROR @ 4777104 ps: (cip_base_vseq.sv:364) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4777104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
8.spi_host_sw_reset.46431995278017851840335418606060719925059211475710177834857116198908249316647
Line 312, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10005038001 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc6062454, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10005038001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
9.spi_host_status_stall.24379003035144478057969734270678782612919610698550031003645371470750949776728
Line 373, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15004148501 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x398c1a54, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 15004148501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=49) has 1 failures:
10.spi_host_speed.114483970082894685658986586422469901635445442564283280540393608266358054970053
Line 473, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_speed/latest/run.log
UVM_FATAL @ 10041452255 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4b195714, Comparison=CompareOpEq, exp_data=0x1, call_count=49)
UVM_INFO @ 10041452255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
10.spi_host_status_stall.54952082080706482370385122440708101991333585817048028830654699133867424395062
Line 413, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10031920841 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd5f25854, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10031920841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
14.spi_host_sw_reset.28626601161422698429627935836469973424326304185224346415908986848845854732458
Line 442, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10295350722 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x15272a94, Comparison=CompareOpEq, exp_data=0x0, call_count=30)
UVM_INFO @ 10295350722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
16.spi_host_sw_reset.92245340574604107151381701959081962565146589007874629845251760883036132146999
Line 352, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/16.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10006086105 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xca58fb94, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10006086105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
20.spi_host_speed.42168399806714652783455091135679568081407574630373526540050403216275256837323
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_speed/latest/run.log
UVM_FATAL @ 10016203814 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9968d254, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10016203814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
20.spi_host_sw_reset.93213065221580653600669979427620130046415947011431226443287420181477863091471
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10017446815 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x764059d4, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10017446815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
25.spi_host_sw_reset.96865379302536027030780127838486746556065523590306352725612631169200113871382
Line 334, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10024830401 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7eeede14, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10024830401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=82) has 1 failures:
27.spi_host_status_stall.13246217271265958197345934905950383074650526697392953342814050308580505004841
Line 933, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10718894130 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2b05fcd4, Comparison=CompareOpEq, exp_data=0x1, call_count=82)
UVM_INFO @ 10718894130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
32.spi_host_idlecsbactive.66017394117980893620387001008656448161214066255337862697344875152890773417773
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/32.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10009197629 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd241d494, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10009197629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: * has 1 failures:
33.spi_host_status_stall.2091504819678768053363385659798827322446322481557446593527288618653586875852
Line 1003, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_status_stall/latest/run.log
UVM_ERROR @ 149619616 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
UVM_INFO @ 149619616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=78) has 1 failures:
34.spi_host_status_stall.78839443135299487506946159878467356809084964430270995255217562780520787856014
Line 891, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/34.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10266812009 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1312c054, Comparison=CompareOpEq, exp_data=0x1, call_count=78)
UVM_INFO @ 10266812009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
35.spi_host_idlecsbactive.33697851439409526625573244678944653855477871799036420050489650415404289955083
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10004773002 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x4c329d54, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10004773002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
36.spi_host_speed.17235353191353328276875374439837099471881330030926181060829976276087955198487
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_speed/latest/run.log
UVM_FATAL @ 10038595095 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4b0b3c94, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
UVM_INFO @ 10038595095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
37.spi_host_spien.58757465733445038394787090863098211612652219954182903664763391395340506122322
Line 367, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/37.spi_host_spien/latest/run.log
UVM_FATAL @ 10057506433 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x48e7e7d4, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10057506433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=95) has 1 failures:
38.spi_host_status_stall.54562560712634267050508129957633465010024766533853428689068727223471070911994
Line 981, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10334322442 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9c13d914, Comparison=CompareOpEq, exp_data=0x1, call_count=95)
UVM_INFO @ 10334322442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
44.spi_host_stress_all.4645633519128476489190017503917784449143696691076748786519389036633244949835
Line 419, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22527808375 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x62a253d4, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 22527808375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
48.spi_host_status_stall.91948679442901703411126607831546960519238219674761557836170687579030493601287
Line 345, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/48.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10009137626 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8a69e6d4, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10009137626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
49.spi_host_sw_reset.57272498105555010269159749369171438985957569288893938882669501521533730629451
Line 369, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15069243237 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x616f4994, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 15069243237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---