SPI_HOST Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 16.900m 15.001ms 36 50 72.00
V1 csr_hw_reset spi_host_csr_hw_reset 8.000s 47.722us 5 5 100.00
V1 csr_rw spi_host_csr_rw 12.000s 42.709us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 20.000s 629.543us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 2.000s 70.596us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 8.000s 186.293us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 12.000s 42.709us 20 20 100.00
spi_host_csr_aliasing 2.000s 70.596us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 15.714us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 7.000s 51.896us 5 5 100.00
V1 TOTAL 101 115 87.83
V2 performance spi_host_performance 8.000s 33.374us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.967m 15.198ms 50 50 100.00
spi_host_error_cmd 15.000s 17.693us 50 50 100.00
spi_host_event 18.550m 100.855ms 50 50 100.00
V2 clock_rate spi_host_speed 11.417m 10.001ms 38 50 76.00
V2 speed spi_host_speed 11.417m 10.001ms 38 50 76.00
V2 chip_select_timing spi_host_speed 11.417m 10.001ms 38 50 76.00
V2 sw_reset spi_host_sw_reset 10.283m 15.069ms 42 50 84.00
V2 passthrough_mode spi_host_passthrough_mode 16.000s 885.500us 50 50 100.00
V2 cpol_cpha spi_host_speed 11.417m 10.001ms 38 50 76.00
V2 full_cycle spi_host_speed 11.417m 10.001ms 38 50 76.00
V2 duplex spi_host_smoke 16.900m 15.001ms 36 50 72.00
V2 tx_rx_only spi_host_smoke 16.900m 15.001ms 36 50 72.00
V2 stress_all spi_host_stress_all 15.000m 22.528ms 43 50 86.00
V2 spien spi_host_spien 7.483m 10.002ms 42 50 84.00
V2 stall spi_host_status_stall 7.883m 10.267ms 32 50 64.00
V2 Idlecsbactive spi_host_idlecsbactive 11.200m 15.002ms 35 50 70.00
V2 data_fifo_status spi_host_overflow_underflow 2.967m 15.198ms 50 50 100.00
V2 alert_test spi_host_alert_test 9.000s 26.812us 50 50 100.00
V2 intr_test spi_host_intr_test 12.000s 39.866us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 14.000s 64.906us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 14.000s 64.906us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 8.000s 47.722us 5 5 100.00
spi_host_csr_rw 12.000s 42.709us 20 20 100.00
spi_host_csr_aliasing 2.000s 70.596us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 61.435us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 8.000s 47.722us 5 5 100.00
spi_host_csr_rw 12.000s 42.709us 20 20 100.00
spi_host_csr_aliasing 2.000s 70.596us 5 5 100.00
spi_host_same_csr_outstanding 8.000s 61.435us 20 20 100.00
V2 TOTAL 622 690 90.14
V2S tl_intg_err spi_host_tl_intg_err 13.000s 153.259us 20 20 100.00
spi_host_sec_cm 2.000s 397.102us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 13.000s 153.259us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 55.833m 184.656ms 1 10 10.00
TOTAL 749 840 89.17

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 9 60.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.77 95.70 100.00 95.07 90.87

Failure Buckets

Past Results