e9b7e615a7| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 17.583m | 15.001ms | 38 | 50 | 76.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 7.000s | 156.372us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 7.000s | 143.726us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 10.000s | 63.710us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 38.150us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 63.039us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 7.000s | 143.726us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 3.000s | 38.150us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 2.000s | 17.983us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 7.000s | 47.928us | 5 | 5 | 100.00 |
| V1 | TOTAL | 103 | 115 | 89.57 | |||
| V2 | performance | spi_host_performance | 4.000s | 463.670us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 3.750m | 70.234ms | 49 | 50 | 98.00 |
| spi_host_error_cmd | 3.000s | 22.922us | 50 | 50 | 100.00 | ||
| spi_host_event | 8.567m | 27.745ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 11.500m | 10.001ms | 40 | 50 | 80.00 |
| V2 | speed | spi_host_speed | 11.500m | 10.001ms | 40 | 50 | 80.00 |
| V2 | chip_select_timing | spi_host_speed | 11.500m | 10.001ms | 40 | 50 | 80.00 |
| V2 | sw_reset | spi_host_sw_reset | 10.467m | 15.688ms | 29 | 50 | 58.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 3.000s | 451.369us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 11.500m | 10.001ms | 40 | 50 | 80.00 |
| V2 | full_cycle | spi_host_speed | 11.500m | 10.001ms | 40 | 50 | 80.00 |
| V2 | duplex | spi_host_smoke | 17.583m | 15.001ms | 38 | 50 | 76.00 |
| V2 | tx_rx_only | spi_host_smoke | 17.583m | 15.001ms | 38 | 50 | 76.00 |
| V2 | stress_all | spi_host_stress_all | 17.183m | 15.001ms | 38 | 50 | 76.00 |
| V2 | spien | spi_host_spien | 16.550m | 15.001ms | 33 | 50 | 66.00 |
| V2 | stall | spi_host_status_stall | 9.800m | 237.840ms | 37 | 50 | 74.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 14.433m | 200.000ms | 40 | 50 | 80.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 3.750m | 70.234ms | 49 | 50 | 98.00 |
| V2 | alert_test | spi_host_alert_test | 3.000s | 41.371us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 12.000s | 18.102us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 158.895us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 158.895us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 7.000s | 156.372us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 143.726us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 38.150us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 33.833us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 7.000s | 156.372us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 7.000s | 143.726us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 3.000s | 38.150us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 7.000s | 33.833us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 606 | 690 | 87.83 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 239.153us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 3.000s | 71.287us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 239.153us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | winbond | winbond | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 56.467m | 100.001ms | 1 | 10 | 10.00 | |
| TOTAL | 735 | 840 | 87.50 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 15 | 15 | 8 | 53.33 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 0 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 90.99 | 90.92 | 83.18 | 92.77 | 89.61 | 95.70 | 100.00 | 95.07 | 90.87 |
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 24 failures:
Test spi_host_spien has 7 failures.
1.spi_host_spien.109918975472785899800200553679801434782518366317095783908299739230395665634009
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_spien/latest/run.log
UVM_FATAL @ 10003447539 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3c2aadd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003447539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.spi_host_spien.88165920635392981062430466363167370448989063654360708534811842456812874426955
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_spien/latest/run.log
UVM_FATAL @ 10001184985 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc1c755d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001184985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test spi_host_stress_all has 2 failures.
3.spi_host_stress_all.3259580631860647430120828308038203243971000569116534642747979245253881287048
Line 354, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15001438115 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x15bf7594, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001438115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.spi_host_stress_all.26193187594678119159873729023236477044157471118064375504858764242003768077323
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/49.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10003896842 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x46d96454, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003896842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_upper_range_clkdiv has 3 failures.
4.spi_host_upper_range_clkdiv.99617374697746023079971733812220872908621592605280491506994380759739640924797
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100000999197 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6fc3e914, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100000999197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.spi_host_upper_range_clkdiv.26942424586428075377338099928263552339097443049867946009311839198164566760224
Line 323, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003816663 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x87920314, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003816663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_smoke has 9 failures.
9.spi_host_smoke.6655351827078580984242459923224996469879837075026253200480213340003697202810
Line 353, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_smoke/latest/run.log
UVM_FATAL @ 15004678555 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4e1ef754, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15004678555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.spi_host_smoke.115258643291954045189321221413954534005230475847822679125025090671845971389068
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_smoke/latest/run.log
UVM_FATAL @ 15001090321 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4d6bd314, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15001090321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test spi_host_speed has 3 failures.
28.spi_host_speed.57442292305403326990891210879417661919186303724179224838098350510782782606547
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_speed/latest/run.log
UVM_FATAL @ 10003796830 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb6a33914, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003796830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.spi_host_speed.28358642007638954430583903385014302649916182740391871981416030937752381140344
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_speed/latest/run.log
UVM_FATAL @ 10000650153 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3b844054, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10000650153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 17 failures:
Test spi_host_speed has 5 failures.
0.spi_host_speed.80948921878999047670062192172348183344397816277012857507715662267494402122928
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log
UVM_FATAL @ 10004686022 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xee44b914, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10004686022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_speed.81555157316368561500917106373770379946905141894739833334160839490952488720449
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_speed/latest/run.log
UVM_FATAL @ 10003653497 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9abb3b54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10003653497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_host_upper_range_clkdiv has 2 failures.
0.spi_host_upper_range_clkdiv.73073204022901871082407005324297098690235714644269427546055585091239716658314
Line 323, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003890281 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa7fd1254, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003890281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_host_upper_range_clkdiv.57109822285516955151769032961431122341344463424208208821442067126711666381605
Line 293, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100005363364 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1e7fa54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100005363364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_spien has 3 failures.
0.spi_host_spien.84601525513832002960589098907465064188739709103627588464005595227966158275647
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log
UVM_FATAL @ 10011715951 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa5ba5d14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10011715951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.spi_host_spien.10539855701524641606436065971021609496225049974471813829616449283204375161419
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_spien/latest/run.log
UVM_FATAL @ 10001478374 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdd74ecd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10001478374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test spi_host_stress_all has 6 failures.
1.spi_host_stress_all.47584493557792769988551507448484826931971602886013478074031353635255184796574
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15009811334 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x5f5c56d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15009811334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_stress_all.108297222869103916807185460572660126571806782526529215522073960363443668985420
Line 341, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10011683829 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf4d8be94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 10011683829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test spi_host_smoke has 1 failures.
17.spi_host_smoke.27436695762470196824956165650966331313482867740986456074887123897062847220516
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_smoke/latest/run.log
UVM_FATAL @ 15000756979 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6b198e54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 15000756979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 5 failures:
11.spi_host_sw_reset.99282469384467085656967536379874986244554781811334909261217435522905025759784
Line 330, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15002923508 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfd6c1414, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 15002923508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.spi_host_sw_reset.50825148731679275213876004587397880932023446808782490761305265215593004344983
Line 334, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15005294542 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x36bf84d4, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 15005294542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 5 failures:
28.spi_host_status_stall.6688726076923427791419517919305866329883082079584005040412643047834164320900
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10014355259 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf742994, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10014355259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.spi_host_status_stall.55436659270306448892411881088424064533347783677838474162481059326373596418831
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10006374957 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x321ef294, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10006374957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
1.spi_host_upper_range_clkdiv.90593522759693032140711249846601684757602728703249970595407689804776021343309
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:7b1968aa-26f2-4a08-9149-571cafb16880
2.spi_host_upper_range_clkdiv.91479379342708717041109664262379491731697382910735770700677052957847617784463
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:8360f84f-1d08-43da-affe-c3e05fe08866
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 4 failures:
23.spi_host_idlecsbactive.51623222296191474233268929208872480713934047621499149444951940902025949552555
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10015133245 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x15c31d4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10015133245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.spi_host_idlecsbactive.47070542779339194542515125572145383429099785864465204254344078859931371296155
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/29.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10016253218 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x15595294, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10016253218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 3 failures:
2.spi_host_sw_reset.105064356784987472871788740824808528017225626729764602587362270768799043593936
Line 320, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10041366581 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x69358714, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10041366581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.spi_host_sw_reset.11320308582802251664099155695906843065566785548861163762157660225701889210915
Line 308, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/18.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10002942530 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2053e4d4, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10002942530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.intr_state reset value: * has 3 failures:
5.spi_host_status_stall.70782156391070264869711041361594142717544178136500060852321432477248019838430
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log
UVM_ERROR @ 3899685 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 3899685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.spi_host_status_stall.51956631476121685720001374897343559479332488521527421162120422747445272127892
Line 351, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_status_stall/latest/run.log
UVM_ERROR @ 3087088 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.intr_state reset value: 0x0
UVM_INFO @ 3087088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 2 failures:
4.spi_host_idlecsbactive.44119757195849974017456570297250621752594357441630017091218114806358978984053
Line 343, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10010431382 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x99506d94, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10010431382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.spi_host_idlecsbactive.69405378281210641181282906799514134111915818604496405942765849669899359501028
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10009456785 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x896b3b94, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10009456785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
12.spi_host_sw_reset.13715072416413404639883812370926030330209447728294242723263740399705706130611
Line 330, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10005875451 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x69940514, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10005875451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.spi_host_sw_reset.3604473008876071217763952990560788345107914909098584037474913338718046616892
Line 332, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/47.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10005771462 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x422ce654, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10005771462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
24.spi_host_idlecsbactive.58030936913092499498119533931760404356749618693377986609951522246001140750414
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/24.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10012849348 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf3a27994, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10012849348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.spi_host_idlecsbactive.95930491800985972951858839520112839901687477358967267479110829631313894131672
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10002200703 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x284c4294, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10002200703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
Test spi_host_spien has 1 failures.
25.spi_host_spien.100506562094200091144350669183621732282005017700781842736743230994557034410583
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/25.spi_host_spien/latest/run.log
UVM_FATAL @ 10010016810 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x19ba5c94, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10010016810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_host_sw_reset has 1 failures.
39.spi_host_sw_reset.8387873086108886205146462866443568582487616184023471765509425872871068421252
Line 362, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/39.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10022145355 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xc4f39714, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10022145355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
0.spi_host_smoke.110778470754993744143292573090665159920555834304790846285598029428428732973588
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log
UVM_FATAL @ 15177881009 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x42ba6494, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 15177881009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=37) has 1 failures:
4.spi_host_sw_reset.56283278421474460616020103079710398140987600181930290177037445763694228164051
Line 454, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/4.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10057529793 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x45162294, Comparison=CompareOpEq, exp_data=0x0, call_count=37)
UVM_INFO @ 10057529793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
6.spi_host_sw_reset.92115482156044713040162487848534843497139388783322843038408271392174340319474
Line 350, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/6.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10001548567 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb0d62d14, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10001548567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
8.spi_host_stress_all.79230891804503912844413504061603398694338286759105013228559468544579474459252
Line 387, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/8.spi_host_stress_all/latest/run.log
UVM_FATAL @ 16080132359 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa7cc9714, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
UVM_INFO @ 16080132359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=34) has 1 failures:
9.spi_host_speed.68953064496069165665591685776005243846742298305714826134470462868412168652166
Line 427, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_speed/latest/run.log
UVM_FATAL @ 10032711679 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd1dc3494, Comparison=CompareOpEq, exp_data=0x1, call_count=34)
UVM_INFO @ 10032711679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
10.spi_host_idlecsbactive.101467921724870276275602548510981297431131964439902343932591767204613314921315
Line 399, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
11.spi_host_smoke.35357999089536360240228832666775088171866184447648875109821507720277567409928
Line 401, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/11.spi_host_smoke/latest/run.log
UVM_FATAL @ 15760162193 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb84e14, Comparison=CompareOpEq, exp_data=0x1, call_count=27)
UVM_INFO @ 15760162193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
12.spi_host_status_stall.77697830361528295707039131324047836531726080833859931814807915506628095244605
Line 361, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10006558866 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xf4f1c54, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10006558866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=32) has 1 failures:
12.spi_host_stress_all.22012348702173733445111179793232168482661502043626797641185845901791603123807
Line 457, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10027230443 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x47d5d454, Comparison=CompareOpEq, exp_data=0x0, call_count=32)
UVM_INFO @ 10027230443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
12.spi_host_spien.102496348980571825397977743475844254743710616450258867349086426049236874870114
Line 383, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/12.spi_host_spien/latest/run.log
UVM_FATAL @ 10020073331 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xafe7ce14, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 10020073331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=36) has 1 failures:
13.spi_host_sw_reset.19215560154068418016976413559223671919238596373383174343914635481452391713723
Line 434, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/13.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15309090451 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6419a914, Comparison=CompareOpEq, exp_data=0x0, call_count=36)
UVM_INFO @ 15309090451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
14.spi_host_idlecsbactive.76804274291530943361822605629000148809275452049868663952472505964967990114153
Line 327, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_idlecsbactive/latest/run.log
UVM_FATAL @ 10007430299 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x7450f514, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10007430299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
17.spi_host_spien.108299726457338997966164016233137542692112439162655860632876640823718994392950
Line 401, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/17.spi_host_spien/latest/run.log
UVM_FATAL @ 10061365565 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb4e7ac94, Comparison=CompareOpEq, exp_data=0x1, call_count=26)
UVM_INFO @ 10061365565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
20.spi_host_sw_reset.108546904507433724261315661115455644989692553957672932447804702253768925290629
Line 421, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10013542581 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x891c6854, Comparison=CompareOpEq, exp_data=0x1, call_count=25)
UVM_INFO @ 10013542581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
20.spi_host_spien.74502314805859885228826526564698553502300908340167330128593539104473613430178
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/20.spi_host_spien/latest/run.log
UVM_FATAL @ 19465344829 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x66f59454, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 19465344829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=28) has 1 failures:
21.spi_host_speed.105687945707567261759795836704292643563233881996462074030002552495520567728837
Line 393, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/21.spi_host_speed/latest/run.log
UVM_FATAL @ 10047536378 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x3921c954, Comparison=CompareOpEq, exp_data=0x1, call_count=28)
UVM_INFO @ 10047536378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=45) has 1 failures:
23.spi_host_sw_reset.78946296715440049419371521772151235905537793022641519983079345417493926301746
Line 524, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/23.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10306725488 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x21ad1d14, Comparison=CompareOpEq, exp_data=0x1, call_count=45)
UVM_INFO @ 10306725488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:364) [spi_host_status_stall_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:
27.spi_host_status_stall.107080433704783585087264897105355936749408284003577688298380829282236297237460
Line 349, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
UVM_ERROR @ 1811626 ps: (cip_base_vseq.sv:364) [uvm_test_top.env.virtual_sequencer.spi_host_status_stall_vseq] Check failed act_pins == exp_pins (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1811626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
28.spi_host_spien.85931762871739543334570528227212875093128938753291274887196463285018538734121
Line 363, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/28.spi_host_spien/latest/run.log
UVM_FATAL @ 17360851264 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6d39fdd4, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 17360851264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=29) has 1 failures:
30.spi_host_sw_reset.63854735844727267139586914744887479480566580311228765033606858781786353118241
Line 429, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 15688186293 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc25f1054, Comparison=CompareOpEq, exp_data=0x0, call_count=29)
UVM_INFO @ 15688186293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=82) has 1 failures:
30.spi_host_status_stall.67854212660061392383886653149966466583697667185183191557212601305619719467880
Line 931, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/30.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10318964396 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x757b9014, Comparison=CompareOpEq, exp_data=0x1, call_count=82)
UVM_INFO @ 10318964396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=36) has 1 failures:
31.spi_host_sw_reset.24127712966400113358852125876685280124617037720628261936551410983415217793293
Line 483, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10042502821 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x57887d4, Comparison=CompareOpEq, exp_data=0x1, call_count=36)
UVM_INFO @ 10042502821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
31.spi_host_status_stall.22946630943444147149469374067100085959902001395293032566637509087991682704681
Line 357, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10006818550 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5cf68dd4, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10006818550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=72) has 1 failures:
35.spi_host_overflow_underflow.99794941700783043786242857472164872883122123664045599155348157636014604104873
Line 279, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_overflow_underflow/latest/run.log
UVM_FATAL @ 70233949973 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1d44aa54, Comparison=CompareOpEq, exp_data=0x0, call_count=72)
UVM_INFO @ 70233949973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=62) has 1 failures:
36.spi_host_stress_all.53028718470075995254652159272422564342080901146973336013140756977630970497064
Line 614, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/36.spi_host_stress_all/latest/run.log
UVM_FATAL @ 29086800415 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4c8a5a54, Comparison=CompareOpEq, exp_data=0x0, call_count=62)
UVM_INFO @ 29086800415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
38.spi_host_spien.95167849708131198939497820963679559009377947335899142209094323981262004714857
Line 413, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/38.spi_host_spien/latest/run.log
UVM_FATAL @ 10049094661 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6936e454, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
UVM_INFO @ 10049094661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
40.spi_host_status_stall.57470256804222754443124662211187780766221874999535358558878791713049793349780
Line 359, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/40.spi_host_status_stall/latest/run.log
UVM_FATAL @ 15139853063 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x260e1514, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 15139853063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
42.spi_host_spien.77933376151466343047013315702822798148076009811840720063372632281554043366528
Line 393, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/42.spi_host_spien/latest/run.log
UVM_FATAL @ 10022126289 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd44c8854, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
UVM_INFO @ 10022126289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
44.spi_host_sw_reset.71216558038147890362109654222302696967529305569917744613226619756630614167534
Line 365, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/44.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10072047184 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2cabbd94, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10072047184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
45.spi_host_sw_reset.59415703162565931007103037415642596900006136982171769932378268164559099928021
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/45.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10003150170 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa5bc9394, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 10003150170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
46.spi_host_sw_reset.74749348161063404027835526894316819383062452254168588571950863863061398467923
Line 344, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 10004058094 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe063ddd4, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10004058094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
46.spi_host_stress_all.82493181341333835112203579748329670439412474875067187057789976021933504067181
Line 452, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/46.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10050217419 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xac71454, Comparison=CompareOpEq, exp_data=0x0, call_count=30)
UVM_INFO @ 10050217419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---