SPI_HOST Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 8.167m 11.609ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 5.000s 47.500us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 34.785us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 632.519us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 47.451us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 5.000s 23.787us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 34.785us 20 20 100.00
spi_host_csr_aliasing 3.000s 47.451us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 16.550us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 53.136us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 8.000s 98.227us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.167m 5.855ms 50 50 100.00
spi_host_error_cmd 3.000s 18.524us 50 50 100.00
spi_host_event 11.633m 61.655ms 50 50 100.00
V2 clock_rate spi_host_speed 28.000s 2.243ms 50 50 100.00
V2 speed spi_host_speed 28.000s 2.243ms 50 50 100.00
V2 chip_select_timing spi_host_speed 28.000s 2.243ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 7.800m 28.291ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 173.723us 50 50 100.00
V2 cpol_cpha spi_host_speed 28.000s 2.243ms 50 50 100.00
V2 full_cycle spi_host_speed 28.000s 2.243ms 50 50 100.00
V2 duplex spi_host_smoke 8.167m 11.609ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 8.167m 11.609ms 50 50 100.00
V2 stress_all spi_host_stress_all 2.417m 9.976ms 50 50 100.00
V2 spien spi_host_spien 2.450m 8.499ms 50 50 100.00
V2 stall spi_host_status_stall 5.383m 9.661ms 49 50 98.00
V2 Idlecsbactive spi_host_idlecsbactive 41.000s 6.218ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.167m 5.855ms 50 50 100.00
V2 alert_test spi_host_alert_test 4.000s 18.105us 50 50 100.00
V2 intr_test spi_host_intr_test 3.000s 17.536us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 6.000s 310.114us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 6.000s 310.114us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 5.000s 47.500us 5 5 100.00
spi_host_csr_rw 3.000s 34.785us 20 20 100.00
spi_host_csr_aliasing 3.000s 47.451us 5 5 100.00
spi_host_same_csr_outstanding 5.000s 35.629us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 5.000s 47.500us 5 5 100.00
spi_host_csr_rw 3.000s 34.785us 20 20 100.00
spi_host_csr_aliasing 3.000s 47.451us 5 5 100.00
spi_host_same_csr_outstanding 5.000s 35.629us 20 20 100.00
V2 TOTAL 689 690 99.86
V2S tl_intg_err spi_host_tl_intg_err 4.000s 259.900us 20 20 100.00
spi_host_sec_cm 3.000s 46.139us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 259.900us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 54.217m 100.003ms 3 10 30.00
TOTAL 832 840 99.05

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 14 93.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results