SPI_HOST Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 8.433m 10.673ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 28.697us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 49.496us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 602.085us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 32.610us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 96.265us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 49.496us 20 20 100.00
spi_host_csr_aliasing 3.000s 32.610us 5 5 100.00
V1 mem_walk spi_host_mem_walk 12.000s 20.681us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 20.026us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 8.000s 99.633us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.700m 12.269ms 50 50 100.00
spi_host_error_cmd 12.000s 15.692us 50 50 100.00
spi_host_event 21.183m 119.857ms 50 50 100.00
V2 clock_rate spi_host_speed 45.000s 4.853ms 50 50 100.00
V2 speed spi_host_speed 45.000s 4.853ms 50 50 100.00
V2 chip_select_timing spi_host_speed 45.000s 4.853ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 3.800m 10.091ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 8.000s 457.340us 50 50 100.00
V2 cpol_cpha spi_host_speed 45.000s 4.853ms 50 50 100.00
V2 full_cycle spi_host_speed 45.000s 4.853ms 50 50 100.00
V2 duplex spi_host_smoke 8.433m 10.673ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 8.433m 10.673ms 50 50 100.00
V2 stress_all spi_host_stress_all 2.267m 5.087ms 50 50 100.00
V2 spien spi_host_spien 8.100m 14.554ms 50 50 100.00
V2 stall spi_host_status_stall 6.233m 16.546ms 48 50 96.00
V2 Idlecsbactive spi_host_idlecsbactive 33.000s 1.241ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.700m 12.269ms 50 50 100.00
V2 alert_test spi_host_alert_test 9.000s 41.938us 50 50 100.00
V2 intr_test spi_host_intr_test 8.000s 30.015us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 11.000s 323.280us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 11.000s 323.280us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 28.697us 5 5 100.00
spi_host_csr_rw 3.000s 49.496us 20 20 100.00
spi_host_csr_aliasing 3.000s 32.610us 5 5 100.00
spi_host_same_csr_outstanding 12.000s 36.376us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 28.697us 5 5 100.00
spi_host_csr_rw 3.000s 49.496us 20 20 100.00
spi_host_csr_aliasing 3.000s 32.610us 5 5 100.00
spi_host_same_csr_outstanding 12.000s 36.376us 20 20 100.00
V2 TOTAL 687 690 99.57
V2S tl_intg_err spi_host_tl_intg_err 13.000s 138.152us 20 20 100.00
spi_host_sec_cm 3.000s 208.939us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 13.000s 138.152us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 52.233m 100.003ms 2 10 20.00
TOTAL 829 840 98.69

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 13 86.67
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results