SPI_HOST Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 7.650m 37.618ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 17.799us 5 5 100.00
V1 csr_rw spi_host_csr_rw 7.000s 38.633us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 8.000s 412.696us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 132.387us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 9.000s 242.201us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 7.000s 38.633us 20 20 100.00
spi_host_csr_aliasing 3.000s 132.387us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 64.059us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 19.025us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 8.000s 94.760us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.250m 20.866ms 50 50 100.00
spi_host_error_cmd 8.000s 29.171us 50 50 100.00
spi_host_event 12.650m 76.536ms 50 50 100.00
V2 clock_rate spi_host_speed 25.000s 493.222us 50 50 100.00
V2 speed spi_host_speed 25.000s 493.222us 50 50 100.00
V2 chip_select_timing spi_host_speed 25.000s 493.222us 50 50 100.00
V2 sw_reset spi_host_sw_reset 2.567m 5.205ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 12.000s 248.312us 50 50 100.00
V2 cpol_cpha spi_host_speed 25.000s 493.222us 50 50 100.00
V2 full_cycle spi_host_speed 25.000s 493.222us 50 50 100.00
V2 duplex spi_host_smoke 7.650m 37.618ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 7.650m 37.618ms 50 50 100.00
V2 stress_all spi_host_stress_all 3.300m 10.006ms 49 50 98.00
V2 spien spi_host_spien 5.167m 25.623ms 50 50 100.00
V2 stall spi_host_status_stall 9.067m 25.551ms 46 50 92.00
V2 Idlecsbactive spi_host_idlecsbactive 24.000s 866.198us 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.250m 20.866ms 50 50 100.00
V2 alert_test spi_host_alert_test 7.000s 17.649us 50 50 100.00
V2 intr_test spi_host_intr_test 9.000s 47.490us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 9.000s 137.246us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 9.000s 137.246us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 17.799us 5 5 100.00
spi_host_csr_rw 7.000s 38.633us 20 20 100.00
spi_host_csr_aliasing 3.000s 132.387us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 71.072us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 17.799us 5 5 100.00
spi_host_csr_rw 7.000s 38.633us 20 20 100.00
spi_host_csr_aliasing 3.000s 132.387us 5 5 100.00
spi_host_same_csr_outstanding 7.000s 71.072us 20 20 100.00
V2 TOTAL 684 690 99.13
V2S tl_intg_err spi_host_tl_intg_err 8.000s 304.179us 20 20 100.00
spi_host_sec_cm 7.000s 882.833us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 8.000s 304.179us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 58.850m 200.000ms 2 10 20.00
TOTAL 826 840 98.33

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results