SPI_HOST Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 8.767m 58.714ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 166.668us 5 5 100.00
V1 csr_rw spi_host_csr_rw 7.000s 32.652us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 9.000s 1.914ms 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 2.000s 21.184us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 8.000s 58.553us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 7.000s 32.652us 20 20 100.00
spi_host_csr_aliasing 2.000s 21.184us 5 5 100.00
V1 mem_walk spi_host_mem_walk 12.000s 32.473us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 8.000s 304.651us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 8.000s 198.797us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.200m 14.556ms 50 50 100.00
spi_host_error_cmd 12.000s 40.177us 50 50 100.00
spi_host_event 14.050m 79.778ms 50 50 100.00
V2 clock_rate spi_host_speed 35.000s 4.354ms 50 50 100.00
V2 speed spi_host_speed 35.000s 4.354ms 50 50 100.00
V2 chip_select_timing spi_host_speed 35.000s 4.354ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 6.500m 15.880ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 13.000s 2.525ms 50 50 100.00
V2 cpol_cpha spi_host_speed 35.000s 4.354ms 50 50 100.00
V2 full_cycle spi_host_speed 35.000s 4.354ms 50 50 100.00
V2 duplex spi_host_smoke 8.767m 58.714ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 8.767m 58.714ms 50 50 100.00
V2 stress_all spi_host_stress_all 2.300m 7.012ms 50 50 100.00
V2 spien spi_host_spien 3.483m 4.443ms 50 50 100.00
V2 stall spi_host_status_stall 12.983m 19.046ms 47 50 94.00
V2 Idlecsbactive spi_host_idlecsbactive 53.000s 4.507ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.200m 14.556ms 50 50 100.00
V2 alert_test spi_host_alert_test 8.000s 48.203us 50 50 100.00
V2 intr_test spi_host_intr_test 12.000s 52.851us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 7.000s 123.046us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 7.000s 123.046us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 166.668us 5 5 100.00
spi_host_csr_rw 7.000s 32.652us 20 20 100.00
spi_host_csr_aliasing 2.000s 21.184us 5 5 100.00
spi_host_same_csr_outstanding 10.000s 28.693us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 166.668us 5 5 100.00
spi_host_csr_rw 7.000s 32.652us 20 20 100.00
spi_host_csr_aliasing 2.000s 21.184us 5 5 100.00
spi_host_same_csr_outstanding 10.000s 28.693us 20 20 100.00
V2 TOTAL 687 690 99.57
V2S tl_intg_err spi_host_tl_intg_err 13.000s 97.294us 20 20 100.00
spi_host_sec_cm 11.000s 37.109us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 13.000s 97.294us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 53.400m 76.126ms 3 10 30.00
TOTAL 830 840 98.81

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 14 93.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results