e4c5daa580
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | spi_host_smoke | 12.100m | 16.506ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | spi_host_csr_hw_reset | 3.000s | 15.649us | 5 | 5 | 100.00 |
V1 | csr_rw | spi_host_csr_rw | 5.000s | 48.176us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | spi_host_csr_bit_bash | 5.000s | 357.296us | 5 | 5 | 100.00 |
V1 | csr_aliasing | spi_host_csr_aliasing | 3.000s | 18.297us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 7.000s | 38.793us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 5.000s | 48.176us | 20 | 20 | 100.00 |
spi_host_csr_aliasing | 3.000s | 18.297us | 5 | 5 | 100.00 | ||
V1 | mem_walk | spi_host_mem_walk | 2.000s | 15.214us | 5 | 5 | 100.00 |
V1 | mem_partial_access | spi_host_mem_partial_access | 2.000s | 38.120us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | performance | spi_host_performance | 8.000s | 107.324us | 50 | 50 | 100.00 |
V2 | error_event_intr | spi_host_overflow_underflow | 2.883m | 13.928ms | 50 | 50 | 100.00 |
spi_host_error_cmd | 12.000s | 21.118us | 50 | 50 | 100.00 | ||
spi_host_event | 14.283m | 32.474ms | 50 | 50 | 100.00 | ||
V2 | clock_rate | spi_host_speed | 25.000s | 507.993us | 50 | 50 | 100.00 |
V2 | speed | spi_host_speed | 25.000s | 507.993us | 50 | 50 | 100.00 |
V2 | chip_select_timing | spi_host_speed | 25.000s | 507.993us | 50 | 50 | 100.00 |
V2 | sw_reset | spi_host_sw_reset | 4.150m | 7.067ms | 49 | 50 | 98.00 |
V2 | passthrough_mode | spi_host_passthrough_mode | 8.000s | 644.534us | 50 | 50 | 100.00 |
V2 | cpol_cpha | spi_host_speed | 25.000s | 507.993us | 50 | 50 | 100.00 |
V2 | full_cycle | spi_host_speed | 25.000s | 507.993us | 50 | 50 | 100.00 |
V2 | duplex | spi_host_smoke | 12.100m | 16.506ms | 50 | 50 | 100.00 |
V2 | tx_rx_only | spi_host_smoke | 12.100m | 16.506ms | 50 | 50 | 100.00 |
V2 | stress_all | spi_host_stress_all | 11.433m | 36.747ms | 47 | 50 | 94.00 |
V2 | spien | spi_host_spien | 3.317m | 15.561ms | 50 | 50 | 100.00 |
V2 | stall | spi_host_status_stall | 7.933m | 44.947ms | 45 | 50 | 90.00 |
V2 | Idlecsbactive | spi_host_idlecsbactive | 33.000s | 4.275ms | 50 | 50 | 100.00 |
V2 | data_fifo_status | spi_host_overflow_underflow | 2.883m | 13.928ms | 50 | 50 | 100.00 |
V2 | alert_test | spi_host_alert_test | 12.000s | 19.268us | 50 | 50 | 100.00 |
V2 | intr_test | spi_host_intr_test | 7.000s | 17.009us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | spi_host_tl_errors | 10.000s | 58.682us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | spi_host_tl_errors | 10.000s | 58.682us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 3.000s | 15.649us | 5 | 5 | 100.00 |
spi_host_csr_rw | 5.000s | 48.176us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 3.000s | 18.297us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 3.000s | 76.950us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | spi_host_csr_hw_reset | 3.000s | 15.649us | 5 | 5 | 100.00 |
spi_host_csr_rw | 5.000s | 48.176us | 20 | 20 | 100.00 | ||
spi_host_csr_aliasing | 3.000s | 18.297us | 5 | 5 | 100.00 | ||
spi_host_same_csr_outstanding | 3.000s | 76.950us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 681 | 690 | 98.70 | |||
V2S | tl_intg_err | spi_host_tl_intg_err | 3.000s | 67.863us | 20 | 20 | 100.00 |
spi_host_sec_cm | 7.000s | 215.170us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 3.000s | 67.863us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | winbond | winbond | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | spi_host_stress_all_with_rand_reset | 0 | 0 | -- | ||
V3 | TOTAL | 0 | 0 | -- | |||
Unmapped tests | spi_host_upper_range_clkdiv | 56.067m | 53.853ms | 4 | 10 | 40.00 | |
TOTAL | 825 | 840 | 98.21 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
N.A. | 1 | 1 | 0 | 0.00 |
V1 | 8 | 8 | 8 | 100.00 |
V2 | 15 | 15 | 12 | 80.00 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 2 | 0 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
91.01 | 90.92 | 83.18 | 92.77 | 89.84 | 95.70 | 100.00 | 95.07 | 90.87 |
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
has 4 failures:
0.spi_host_upper_range_clkdiv.41901204963070989512157260560397440032659521902698823296525878031367688217462
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100008300905 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x2c141594, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100008300905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.spi_host_upper_range_clkdiv.2874018579375753951696002596858083437898165852872450067056929625609332266623
Line 313, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100007980501 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x36c7b314, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100007980501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25)
has 3 failures:
2.spi_host_stress_all.3671627835053459979312340925444680772767534413848307908661348412599771817520
Line 534, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/2.spi_host_stress_all/latest/run.log
UVM_FATAL @ 10039799413 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x49142394, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10039799413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.spi_host_stress_all.51895329189831403748139787949007987424123841911822882666607316410834505270351
Line 451, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/5.spi_host_stress_all/latest/run.log
UVM_FATAL @ 15044276509 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x607af7d4, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 15044276509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job spi_host-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 2 failures:
3.spi_host_upper_range_clkdiv.81475965288621270680304644185139759940096384511964535907026870618239666754087
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:b52ce18a-2d0c-42b3-a502-02aa924f1d44
9.spi_host_upper_range_clkdiv.20857989639244174059699895092095121232353682605893514230417960578421422772373
Log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
Job ID: smart:5f5c6cc5-38c4-4d36-ab8b-87c52005f062
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=92)
has 1 failures:
1.spi_host_status_stall.35128398770273825456342662042952037286278569932452261290632688093792014950475
Line 943, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log
UVM_FATAL @ 11244764571 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2e9586d4, Comparison=CompareOpEq, exp_data=0x1, call_count=92)
UVM_INFO @ 11244764571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=75)
has 1 failures:
10.spi_host_status_stall.61059503159964500303005254769707173143797935561219551191638685484013219311887
Line 846, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log
UVM_FATAL @ 11967990988 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x10446d14, Comparison=CompareOpEq, exp_data=0x1, call_count=75)
UVM_INFO @ 11967990988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=85)
has 1 failures:
14.spi_host_status_stall.26422550926582820665806113212509239113885707928350514138034151097198638707101
Line 924, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/14.spi_host_status_stall/latest/run.log
UVM_FATAL @ 12469746651 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2f719c54, Comparison=CompareOpEq, exp_data=0x1, call_count=85)
UVM_INFO @ 12469746651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=86)
has 1 failures:
15.spi_host_status_stall.81594613026749123208152704462988895324461798924487052639171664248619298505160
Line 921, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10276697935 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x52077454, Comparison=CompareOpEq, exp_data=0x1, call_count=86)
UVM_INFO @ 10276697935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=36)
has 1 failures:
33.spi_host_sw_reset.31292846934519680134994370332440340354639424783072942644837893324959400599739
Line 453, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/33.spi_host_sw_reset/latest/run.log
UVM_FATAL @ 17889649925 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf4956154, Comparison=CompareOpEq, exp_data=0x0, call_count=36)
UVM_INFO @ 17889649925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=81)
has 1 failures:
35.spi_host_status_stall.108095433949426918297996788896071388312939281260403245918296010144069660311541
Line 899, in log /container/opentitan-public/scratch/os_regression/spi_host-sim-xcelium/35.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10210661921 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa7b646d4, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
UVM_INFO @ 10210661921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---