SPI_HOST Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 12.100m 16.506ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 15.649us 5 5 100.00
V1 csr_rw spi_host_csr_rw 5.000s 48.176us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 357.296us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 18.297us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 7.000s 38.793us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 5.000s 48.176us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.297us 5 5 100.00
V1 mem_walk spi_host_mem_walk 2.000s 15.214us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 38.120us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 8.000s 107.324us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.883m 13.928ms 50 50 100.00
spi_host_error_cmd 12.000s 21.118us 50 50 100.00
spi_host_event 14.283m 32.474ms 50 50 100.00
V2 clock_rate spi_host_speed 25.000s 507.993us 50 50 100.00
V2 speed spi_host_speed 25.000s 507.993us 50 50 100.00
V2 chip_select_timing spi_host_speed 25.000s 507.993us 50 50 100.00
V2 sw_reset spi_host_sw_reset 4.150m 7.067ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 8.000s 644.534us 50 50 100.00
V2 cpol_cpha spi_host_speed 25.000s 507.993us 50 50 100.00
V2 full_cycle spi_host_speed 25.000s 507.993us 50 50 100.00
V2 duplex spi_host_smoke 12.100m 16.506ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 12.100m 16.506ms 50 50 100.00
V2 stress_all spi_host_stress_all 11.433m 36.747ms 47 50 94.00
V2 spien spi_host_spien 3.317m 15.561ms 50 50 100.00
V2 stall spi_host_status_stall 7.933m 44.947ms 45 50 90.00
V2 Idlecsbactive spi_host_idlecsbactive 33.000s 4.275ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.883m 13.928ms 50 50 100.00
V2 alert_test spi_host_alert_test 12.000s 19.268us 50 50 100.00
V2 intr_test spi_host_intr_test 7.000s 17.009us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 10.000s 58.682us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 10.000s 58.682us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 15.649us 5 5 100.00
spi_host_csr_rw 5.000s 48.176us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.297us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 76.950us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 15.649us 5 5 100.00
spi_host_csr_rw 5.000s 48.176us 20 20 100.00
spi_host_csr_aliasing 3.000s 18.297us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 76.950us 20 20 100.00
V2 TOTAL 681 690 98.70
V2S tl_intg_err spi_host_tl_intg_err 3.000s 67.863us 20 20 100.00
spi_host_sec_cm 7.000s 215.170us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 3.000s 67.863us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 56.067m 53.853ms 4 10 40.00
TOTAL 825 840 98.21

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results