SPI_HOST Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: 5fd4ecc0fc

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.500m 37.454ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 61.537us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 15.570us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 361.507us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 7.000s 17.789us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 4.000s 38.495us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 15.570us 20 20 100.00
spi_host_csr_aliasing 7.000s 17.789us 5 5 100.00
V1 mem_walk spi_host_mem_walk 4.000s 17.630us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 4.000s 26.862us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 7.000s 32.958us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 1.700m 4.471ms 50 50 100.00
spi_host_error_cmd 3.000s 18.300us 50 50 100.00
spi_host_event 18.267m 27.266ms 50 50 100.00
V2 clock_rate spi_host_speed 26.000s 2.031ms 50 50 100.00
V2 speed spi_host_speed 26.000s 2.031ms 50 50 100.00
V2 chip_select_timing spi_host_speed 26.000s 2.031ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 2.500m 4.909ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 13.000s 1.236ms 50 50 100.00
V2 cpol_cpha spi_host_speed 26.000s 2.031ms 50 50 100.00
V2 full_cycle spi_host_speed 26.000s 2.031ms 50 50 100.00
V2 duplex spi_host_smoke 9.500m 37.454ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 9.500m 37.454ms 50 50 100.00
V2 stress_all spi_host_stress_all 2.717m 3.694ms 50 50 100.00
V2 spien spi_host_spien 4.750m 14.817ms 50 50 100.00
V2 stall spi_host_status_stall 11.517m 27.687ms 46 50 92.00
V2 Idlecsbactive spi_host_idlecsbactive 1.133m 3.847ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 1.700m 4.471ms 50 50 100.00
V2 alert_test spi_host_alert_test 3.000s 37.826us 50 50 100.00
V2 intr_test spi_host_intr_test 17.000s 47.339us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 5.000s 150.281us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 5.000s 150.281us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 61.537us 5 5 100.00
spi_host_csr_rw 3.000s 15.570us 20 20 100.00
spi_host_csr_aliasing 7.000s 17.789us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 34.682us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 61.537us 5 5 100.00
spi_host_csr_rw 3.000s 15.570us 20 20 100.00
spi_host_csr_aliasing 7.000s 17.789us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 34.682us 20 20 100.00
V2 TOTAL 686 690 99.42
V2S tl_intg_err spi_host_tl_intg_err 8.000s 231.601us 20 20 100.00
spi_host_sec_cm 2.000s 287.073us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 8.000s 231.601us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 57.317m 100.003ms 1 10 10.00
TOTAL 827 840 98.45

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 14 93.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results