SPI_HOST Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 6.633m 17.578ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 49.470us 5 5 100.00
V1 csr_rw spi_host_csr_rw 3.000s 30.584us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 161.050us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 27.403us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 41.959us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 30.584us 20 20 100.00
spi_host_csr_aliasing 4.000s 27.403us 5 5 100.00
V1 mem_walk spi_host_mem_walk 4.000s 47.171us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 30.254us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 8.000s 30.939us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.883m 3.634ms 50 50 100.00
spi_host_error_cmd 7.000s 18.262us 50 50 100.00
spi_host_event 12.200m 68.719ms 50 50 100.00
V2 clock_rate spi_host_speed 32.000s 471.713us 50 50 100.00
V2 speed spi_host_speed 32.000s 471.713us 50 50 100.00
V2 chip_select_timing spi_host_speed 32.000s 471.713us 50 50 100.00
V2 sw_reset spi_host_sw_reset 4.083m 8.013ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 14.000s 390.367us 50 50 100.00
V2 cpol_cpha spi_host_speed 32.000s 471.713us 50 50 100.00
V2 full_cycle spi_host_speed 32.000s 471.713us 50 50 100.00
V2 duplex spi_host_smoke 6.633m 17.578ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 6.633m 17.578ms 50 50 100.00
V2 stress_all spi_host_stress_all 1.850m 7.015ms 50 50 100.00
V2 spien spi_host_spien 4.850m 6.840ms 49 50 98.00
V2 stall spi_host_status_stall 8.167m 23.505ms 48 50 96.00
V2 Idlecsbactive spi_host_idlecsbactive 35.000s 5.384ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.883m 3.634ms 50 50 100.00
V2 alert_test spi_host_alert_test 12.000s 15.435us 50 50 100.00
V2 intr_test spi_host_intr_test 7.000s 54.674us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 8.000s 60.823us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 8.000s 60.823us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 49.470us 5 5 100.00
spi_host_csr_rw 3.000s 30.584us 20 20 100.00
spi_host_csr_aliasing 4.000s 27.403us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 27.225us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 49.470us 5 5 100.00
spi_host_csr_rw 3.000s 30.584us 20 20 100.00
spi_host_csr_aliasing 4.000s 27.403us 5 5 100.00
spi_host_same_csr_outstanding 3.000s 27.225us 20 20 100.00
V2 TOTAL 687 690 99.57
V2S tl_intg_err spi_host_tl_intg_err 7.000s 339.659us 20 20 100.00
spi_host_sec_cm 3.000s 327.237us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 7.000s 339.659us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 55.517m 200.000ms 3 10 30.00
TOTAL 830 840 98.81

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 13 86.67
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.77 95.70 100.00 95.07 90.87

Failure Buckets

Past Results