SPI_HOST Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 9.883m 46.825ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 32.000s 30.176us 5 5 100.00
V1 csr_rw spi_host_csr_rw 2.017m 94.486us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 33.000s 124.264us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 28.000s 19.356us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 2.050m 40.341us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 2.017m 94.486us 20 20 100.00
spi_host_csr_aliasing 28.000s 19.356us 5 5 100.00
V1 mem_walk spi_host_mem_walk 36.000s 42.220us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 1.133m 19.985us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 1.983m 43.836us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 3.933m 13.540ms 50 50 100.00
spi_host_error_cmd 2.267m 57.191us 50 50 100.00
spi_host_event 16.433m 30.016ms 50 50 100.00
V2 clock_rate spi_host_speed 3.217m 2.121ms 50 50 100.00
V2 speed spi_host_speed 3.217m 2.121ms 50 50 100.00
V2 chip_select_timing spi_host_speed 3.217m 2.121ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 3.067m 9.438ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 3.967m 723.304us 50 50 100.00
V2 cpol_cpha spi_host_speed 3.217m 2.121ms 50 50 100.00
V2 full_cycle spi_host_speed 3.217m 2.121ms 50 50 100.00
V2 duplex spi_host_smoke 9.883m 46.825ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 9.883m 46.825ms 50 50 100.00
V2 stress_all spi_host_stress_all 3.483m 5.279ms 50 50 100.00
V2 spien spi_host_spien 5.767m 109.615ms 50 50 100.00
V2 stall spi_host_status_stall 3.767m 19.873ms 46 50 92.00
V2 Idlecsbactive spi_host_idlecsbactive 2.000m 6.434ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 3.933m 13.540ms 50 50 100.00
V2 alert_test spi_host_alert_test 4.083m 47.184us 50 50 100.00
V2 intr_test spi_host_intr_test 1.983m 25.193us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 1.967m 90.636us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 1.967m 90.636us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 32.000s 30.176us 5 5 100.00
spi_host_csr_rw 2.017m 94.486us 20 20 100.00
spi_host_csr_aliasing 28.000s 19.356us 5 5 100.00
spi_host_same_csr_outstanding 2.083m 27.615us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 32.000s 30.176us 5 5 100.00
spi_host_csr_rw 2.017m 94.486us 20 20 100.00
spi_host_csr_aliasing 28.000s 19.356us 5 5 100.00
spi_host_same_csr_outstanding 2.083m 27.615us 20 20 100.00
V2 TOTAL 686 690 99.42
V2S tl_intg_err spi_host_tl_intg_err 2.050m 90.699us 20 20 100.00
spi_host_sec_cm 17.000s 101.173us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 2.050m 90.699us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 53.817m 100.004ms 1 10 10.00
TOTAL 827 840 98.45

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 14 93.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results