SPI_HOST Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 7.500m 20.189ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 106.864us 5 5 100.00
V1 csr_rw spi_host_csr_rw 46.000s 301.644us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 6.000s 127.097us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 75.693us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 49.000s 75.740us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 46.000s 301.644us 20 20 100.00
spi_host_csr_aliasing 4.000s 75.693us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 16.991us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 4.000s 18.173us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 1.467m 97.714us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.333m 6.873ms 50 50 100.00
spi_host_error_cmd 1.450m 54.354us 50 50 100.00
spi_host_event 13.383m 90.793ms 50 50 100.00
V2 clock_rate spi_host_speed 1.700m 3.532ms 50 50 100.00
V2 speed spi_host_speed 1.700m 3.532ms 50 50 100.00
V2 chip_select_timing spi_host_speed 1.700m 3.532ms 50 50 100.00
V2 sw_reset spi_host_sw_reset 4.833m 14.841ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 1.483m 469.221us 50 50 100.00
V2 cpol_cpha spi_host_speed 1.700m 3.532ms 50 50 100.00
V2 full_cycle spi_host_speed 1.700m 3.532ms 50 50 100.00
V2 duplex spi_host_smoke 7.500m 20.189ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 7.500m 20.189ms 50 50 100.00
V2 stress_all spi_host_stress_all 2.067m 6.856ms 49 50 98.00
V2 spien spi_host_spien 4.017m 32.477ms 49 50 98.00
V2 stall spi_host_status_stall 7.833m 10.227ms 49 50 98.00
V2 Idlecsbactive spi_host_idlecsbactive 1.733m 1.572ms 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.333m 6.873ms 50 50 100.00
V2 alert_test spi_host_alert_test 1.450m 50.642us 50 50 100.00
V2 intr_test spi_host_intr_test 54.000s 27.745us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 44.000s 621.516us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 44.000s 621.516us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 106.864us 5 5 100.00
spi_host_csr_rw 46.000s 301.644us 20 20 100.00
spi_host_csr_aliasing 4.000s 75.693us 5 5 100.00
spi_host_same_csr_outstanding 45.000s 31.889us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 106.864us 5 5 100.00
spi_host_csr_rw 46.000s 301.644us 20 20 100.00
spi_host_csr_aliasing 4.000s 75.693us 5 5 100.00
spi_host_same_csr_outstanding 45.000s 31.889us 20 20 100.00
V2 TOTAL 686 690 99.42
V2S tl_intg_err spi_host_tl_intg_err 57.000s 484.896us 20 20 100.00
spi_host_sec_cm 28.000s 495.596us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 57.000s 484.896us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 56.017m 100.003ms 1 10 10.00
TOTAL 827 840 98.45

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 11 73.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.03 90.96 83.26 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results