SPI_HOST Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 8.283m 44.527ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 25.000s 29.064us 5 5 100.00
V1 csr_rw spi_host_csr_rw 30.000s 18.571us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 27.000s 932.074us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 23.000s 208.844us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 39.000s 33.271us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 30.000s 18.571us 20 20 100.00
spi_host_csr_aliasing 23.000s 208.844us 5 5 100.00
V1 mem_walk spi_host_mem_walk 14.000s 16.070us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 25.000s 41.111us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 1.400m 31.932us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 2.117m 5.223ms 50 50 100.00
spi_host_error_cmd 1.883m 38.293us 50 50 100.00
spi_host_event 8.517m 69.984ms 50 50 100.00
V2 clock_rate spi_host_speed 1.467m 514.463us 50 50 100.00
V2 speed spi_host_speed 1.467m 514.463us 50 50 100.00
V2 chip_select_timing spi_host_speed 1.467m 514.463us 50 50 100.00
V2 sw_reset spi_host_sw_reset 5.233m 20.734ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 1.767m 198.212us 50 50 100.00
V2 cpol_cpha spi_host_speed 1.467m 514.463us 50 50 100.00
V2 full_cycle spi_host_speed 1.467m 514.463us 50 50 100.00
V2 duplex spi_host_smoke 8.283m 44.527ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 8.283m 44.527ms 50 50 100.00
V2 stress_all spi_host_stress_all 1.917m 12.273ms 49 50 98.00
V2 spien spi_host_spien 1.533m 3.149ms 49 50 98.00
V2 stall spi_host_status_stall 5.867m 8.580ms 49 50 98.00
V2 Idlecsbactive spi_host_idlecsbactive 2.100m 118.237us 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 2.117m 5.223ms 50 50 100.00
V2 alert_test spi_host_alert_test 1.717m 31.626us 50 50 100.00
V2 intr_test spi_host_intr_test 28.000s 23.694us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 28.000s 24.139us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 28.000s 24.139us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 25.000s 29.064us 5 5 100.00
spi_host_csr_rw 30.000s 18.571us 20 20 100.00
spi_host_csr_aliasing 23.000s 208.844us 5 5 100.00
spi_host_same_csr_outstanding 30.000s 27.922us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 25.000s 29.064us 5 5 100.00
spi_host_csr_rw 30.000s 18.571us 20 20 100.00
spi_host_csr_aliasing 23.000s 208.844us 5 5 100.00
spi_host_same_csr_outstanding 30.000s 27.922us 20 20 100.00
V2 TOTAL 687 690 99.57
V2S tl_intg_err spi_host_tl_intg_err 27.000s 519.830us 20 20 100.00
spi_host_sec_cm 1.433m 121.663us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 27.000s 519.830us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 52.750m 100.005ms 6 10 60.00
TOTAL 833 840 99.17

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.02 90.92 83.18 92.77 89.92 95.70 100.00 95.07 90.87

Failure Buckets

Past Results