SPI_HOST Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 8.217m 20.946ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 96.124us 5 5 100.00
V1 csr_rw spi_host_csr_rw 1.550m 16.517us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 59.376us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 24.023us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 1.517m 23.552us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 1.550m 16.517us 20 20 100.00
spi_host_csr_aliasing 4.000s 24.023us 5 5 100.00
V1 mem_walk spi_host_mem_walk 5.000s 17.825us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 5.000s 28.897us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 1.517m 63.606us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 1.633m 4.957ms 50 50 100.00
spi_host_error_cmd 1.583m 68.917us 50 50 100.00
spi_host_event 14.683m 42.965ms 50 50 100.00
V2 clock_rate spi_host_speed 1.550m 795.481us 49 50 98.00
V2 speed spi_host_speed 1.550m 795.481us 49 50 98.00
V2 chip_select_timing spi_host_speed 1.550m 795.481us 49 50 98.00
V2 sw_reset spi_host_sw_reset 7.183m 10.030ms 49 50 98.00
V2 passthrough_mode spi_host_passthrough_mode 51.000s 251.664us 50 50 100.00
V2 cpol_cpha spi_host_speed 1.550m 795.481us 49 50 98.00
V2 full_cycle spi_host_speed 1.550m 795.481us 49 50 98.00
V2 duplex spi_host_smoke 8.217m 20.946ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 8.217m 20.946ms 50 50 100.00
V2 stress_all spi_host_stress_all 5.500m 15.029ms 49 50 98.00
V2 spien spi_host_spien 1.500m 26.306ms 50 50 100.00
V2 stall spi_host_status_stall 6.367m 28.318ms 48 50 96.00
V2 Idlecsbactive spi_host_idlecsbactive 1.033m 994.797us 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 1.633m 4.957ms 50 50 100.00
V2 alert_test spi_host_alert_test 1.583m 57.501us 50 50 100.00
V2 intr_test spi_host_intr_test 1.300m 34.725us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 55.000s 216.132us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 55.000s 216.132us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 96.124us 5 5 100.00
spi_host_csr_rw 1.550m 16.517us 20 20 100.00
spi_host_csr_aliasing 4.000s 24.023us 5 5 100.00
spi_host_same_csr_outstanding 1.900m 65.066us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 96.124us 5 5 100.00
spi_host_csr_rw 1.550m 16.517us 20 20 100.00
spi_host_csr_aliasing 4.000s 24.023us 5 5 100.00
spi_host_same_csr_outstanding 1.900m 65.066us 20 20 100.00
V2 TOTAL 685 690 99.28
V2S tl_intg_err spi_host_tl_intg_err 1.533m 71.389us 20 20 100.00
spi_host_sec_cm 1.233m 64.391us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 1.533m 71.389us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 54.717m 100.004ms 4 10 40.00
TOTAL 829 840 98.69

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 11 73.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.03 90.96 83.26 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results