SPI_HOST Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 7.533m 22.971ms 50 50 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 4.000s 57.338us 5 5 100.00
V1 csr_rw spi_host_csr_rw 1.033m 179.682us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 7.000s 781.274us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 25.143us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 54.000s 43.032us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 1.033m 179.682us 20 20 100.00
spi_host_csr_aliasing 4.000s 25.143us 5 5 100.00
V1 mem_walk spi_host_mem_walk 3.000s 19.961us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 4.000s 27.221us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 performance spi_host_performance 39.000s 31.512us 50 50 100.00
V2 error_event_intr spi_host_overflow_underflow 1.200m 4.004ms 50 50 100.00
spi_host_error_cmd 20.000s 48.894us 50 50 100.00
spi_host_event 11.883m 40.083ms 50 50 100.00
V2 clock_rate spi_host_speed 59.000s 851.261us 49 50 98.00
V2 speed spi_host_speed 59.000s 851.261us 49 50 98.00
V2 chip_select_timing spi_host_speed 59.000s 851.261us 49 50 98.00
V2 sw_reset spi_host_sw_reset 3.333m 7.656ms 50 50 100.00
V2 passthrough_mode spi_host_passthrough_mode 40.000s 1.764ms 50 50 100.00
V2 cpol_cpha spi_host_speed 59.000s 851.261us 49 50 98.00
V2 full_cycle spi_host_speed 59.000s 851.261us 49 50 98.00
V2 duplex spi_host_smoke 7.533m 22.971ms 50 50 100.00
V2 tx_rx_only spi_host_smoke 7.533m 22.971ms 50 50 100.00
V2 stress_all spi_host_stress_all 3.633m 10.001ms 49 50 98.00
V2 spien spi_host_spien 3.600m 48.452ms 50 50 100.00
V2 stall spi_host_status_stall 6.383m 19.926ms 45 50 90.00
V2 Idlecsbactive spi_host_idlecsbactive 42.000s 267.376us 50 50 100.00
V2 data_fifo_status spi_host_overflow_underflow 1.200m 4.004ms 50 50 100.00
V2 alert_test spi_host_alert_test 33.000s 17.402us 50 50 100.00
V2 intr_test spi_host_intr_test 58.000s 37.690us 50 50 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 57.000s 84.014us 20 20 100.00
V2 tl_d_illegal_access spi_host_tl_errors 57.000s 84.014us 20 20 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 4.000s 57.338us 5 5 100.00
spi_host_csr_rw 1.033m 179.682us 20 20 100.00
spi_host_csr_aliasing 4.000s 25.143us 5 5 100.00
spi_host_same_csr_outstanding 1.083m 55.185us 20 20 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 4.000s 57.338us 5 5 100.00
spi_host_csr_rw 1.033m 179.682us 20 20 100.00
spi_host_csr_aliasing 4.000s 25.143us 5 5 100.00
spi_host_same_csr_outstanding 1.083m 55.185us 20 20 100.00
V2 TOTAL 683 690 98.99
V2S tl_intg_err spi_host_tl_intg_err 57.000s 213.143us 20 20 100.00
spi_host_sec_cm 3.000s 231.956us 5 5 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 57.000s 213.143us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 52.250m 100.005ms 3 10 30.00
TOTAL 826 840 98.33

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 8 100.00
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
91.01 90.92 83.18 92.77 89.84 95.70 100.00 95.07 90.87

Failure Buckets

Past Results