SPI_HOST Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	8.867m	21.913ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.783m	23.040us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	1.733m	18.095us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	1.817m	1.096ms	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.600m	18.450us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.533m	402.864us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.733m	18.095us	20	20	100.00
		spi_host_csr_aliasing	1.600m	18.450us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	1.550m	19.931us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.767m	17.639us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	2.117m	95.861us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.483m	3.026ms	50	50	100.00
		spi_host_error_cmd	1.800m	18.910us	50	50	100.00
		spi_host_event	12.900m	23.040ms	50	50	100.00
V2	clock_rate	spi_host_speed	1.317m	406.491us	50	50	100.00
V2	speed	spi_host_speed	1.317m	406.491us	50	50	100.00
V2	chip_select_timing	spi_host_speed	1.317m	406.491us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	2.250m	849.765us	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.983m	519.372us	50	50	100.00
V2	cpol_cpha	spi_host_speed	1.317m	406.491us	50	50	100.00
V2	full_cycle	spi_host_speed	1.317m	406.491us	50	50	100.00
V2	duplex	spi_host_smoke	8.867m	21.913ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	8.867m	21.913ms	50	50	100.00
V2	stress_all	spi_host_stress_all	4.350m	10.011ms	49	50	98.00
V2	spien	spi_host_spien	5.700m	7.288ms	50	50	100.00
V2	stall	spi_host_status_stall	6.250m	9.972ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.567m	240.077us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.483m	3.026ms	50	50	100.00
V2	alert_test	spi_host_alert_test	1.150m	103.772us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.100m	26.451us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	1.583m	252.234us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	1.583m	252.234us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.783m	23.040us	5	5	100.00
		spi_host_csr_rw	1.733m	18.095us	20	20	100.00
		spi_host_csr_aliasing	1.600m	18.450us	5	5	100.00
		spi_host_same_csr_outstanding	1.933m	47.306us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.783m	23.040us	5	5	100.00
		spi_host_csr_rw	1.733m	18.095us	20	20	100.00
		spi_host_csr_aliasing	1.600m	18.450us	5	5	100.00
		spi_host_same_csr_outstanding	1.933m	47.306us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	1.933m	98.195us	20	20	100.00
		spi_host_sec_cm	1.567m	146.707us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.933m	98.195us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_host_upper_range_clkdiv	44.917m	100.002ms	3	10	30.00
		TOTAL			831	840	98.93

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	15	15	13	86.67
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.01	90.92	83.18	92.77	89.84	95.70	100.00	95.07	90.87

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 6 failures:

  • Test spi_host_upper_range_clkdiv has 6 failures.

    • 0.spi_host_upper_range_clkdiv.102251657358832458144814071057113259790856939107173239541250572270761999921406
      Line 136, in log /workspaces/repo/scratch/os_regression_2024_09_08/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100005044699 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x192ff954, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100005044699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.spi_host_upper_range_clkdiv.75545423346131575279127947938102049999938996494282457864270459525580842553779
      Line 109, in log /workspaces/repo/scratch/os_regression_2024_09_08/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100002585464 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xfe5c3e94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100002585464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=90) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 4.spi_host_status_stall.30928017390124295175370458161997824064469028554107263073449171525459025068739
      Line 742, in log /workspaces/repo/scratch/os_regression_2024_09_08/spi_host-sim-xcelium/4.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 10076440860 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa5a22f94, Comparison=CompareOpEq, exp_data=0x1, call_count=90)
        UVM_INFO @ 10076440860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 6.spi_host_upper_range_clkdiv.97565239622834514873849370606716220138477954380003479729216434597192805916191
      Log /workspaces/repo/scratch/os_regression_2024_09_08/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log

        Job timed out after 60 minutes
      

• UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:

  • Test spi_host_stress_all has 1 failures.

    • 43.spi_host_stress_all.105495284554808615827896325374969660457287699968610753339906473748384987132916
      Line 191, in log /workspaces/repo/scratch/os_regression_2024_09_08/spi_host-sim-xcelium/43.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 10010909703 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x80737a14, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
        UVM_INFO @ 10010909703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.09.05_04.23.55
• 2024.09.02_11.33.33
• 2024.08.29_23.15.39
• 2024.08.28_06.59.09
• 2024.08.26_02.20.40
• 2024.08.24_20.17.36
• 2024.08.22_14.19.17