SRAM_CTRL/MAIN Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.023m	473.627us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	15.839us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	26.229us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.280s	418.118us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	22.641us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.870s	4.910ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	26.229us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	22.641us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.514m	275.239ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.929m	19.899ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	36.246m	83.745ms	48	50	96.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.467m	14.833ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	48.382m	155.765ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	31.358m	20.711ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.009m	75.483ms	50	50	100.00
V2	executable	sram_ctrl_executable	32.497m	243.186ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.955m	2.866ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.899m	80.573ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.920m	4.235ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	3.031m	943.422us	50	50	100.00
V2	regwen	sram_ctrl_regwen	34.324m	35.120ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.490s	3.707ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.663h	403.843ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.720s	39.836us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.950s	1.728ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.950s	1.728ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	15.839us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	26.229us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	22.641us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	100.212us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	15.839us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	26.229us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	22.641us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	100.212us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	56.760s	28.187ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.310s	805.787us	5	5	100.00
		sram_ctrl_tl_intg_err	2.580s	396.329us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.310s	805.787us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.580s	396.329us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	34.324m	35.120ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	26.229us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.497m	243.186ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.497m	243.186ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.497m	243.186ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.009m	75.483ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	56.760s	28.187ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.023m	473.627us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.023m	473.627us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.497m	243.186ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.310s	805.787us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.009m	75.483ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.310s	805.787us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.310s	805.787us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.023m	473.627us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.310s	805.787us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.722m	1.306ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.41	100.00	97.91	100.00	100.00	99.72	99.70	98.52

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test sram_ctrl_multiple_keys has 2 failures.

    • 6.sram_ctrl_multiple_keys.62663251914830344313419145498999780854708773501789289408662710170991606721982
      Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/6.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 72057821908 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x612ae44e
        UVM_INFO @ 72057821908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.sram_ctrl_multiple_keys.49488166623356206152618103759967784714211763487938706240820005857446120174154
      Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 77526121242 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xdf122695
        UVM_INFO @ 77526121242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 20.sram_ctrl_stress_all.31610467522361931632007532620388103791988003494754246050957630581983453723072
      Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 16642385950 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x5cd6d5f7
        UVM_INFO @ 16642385950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_regwen has 1 failures.

    • 22.sram_ctrl_regwen.85988115931015072486314599921666772300295350963371567587991546612429989468627
      Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_regwen/latest/run.log

        UVM_FATAL @ 19788633437 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xf08bea67
        UVM_INFO @ 19788633437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:827) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.sram_ctrl_stress_all_with_rand_reset.45031520530597222471135999182915344625120472154831308561043328560646734787745
      Line 350, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2232979813 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2232979813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.03.18_04.49.27
• 2024.03.15_00.23.05
• 2024.03.13_04.19.00
• 2024.03.11_03.36.41
• 2024.03.08_05.24.35
• 2024.03.06_08.26.51
• 2024.03.04_05.12.37