SRAM_CTRL/MAIN Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.498m	1.298ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	25.072us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	19.397us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.290s	188.657us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	19.841us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.290s	1.413ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	19.397us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	19.841us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.480m	20.641ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.778m	17.356ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	32.525m	32.727ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.266m	22.821ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	48.041m	344.938ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	35.260m	36.239ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.964m	75.507ms	50	50	100.00
V2	executable	sram_ctrl_executable	32.762m	173.799ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	3.343m	1.803ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.326m	361.894ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.345m	7.617ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.746m	822.950us	50	50	100.00
V2	regwen	sram_ctrl_regwen	37.105m	17.499ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.130s	6.666ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.925h	1.170s	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.720s	14.540us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.770s	552.637us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.770s	552.637us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	25.072us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	19.397us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	19.841us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	27.186us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	25.072us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	19.397us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	19.841us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	27.186us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	56.660s	28.121ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.040s	1.221ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.690s	537.520us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.040s	1.221ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.690s	537.520us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	37.105m	17.499ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	19.397us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.762m	173.799ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.762m	173.799ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.762m	173.799ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.964m	75.507ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	56.660s	28.121ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.498m	1.298ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.498m	1.298ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.762m	173.799ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.040s	1.221ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.964m	75.507ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.040s	1.221ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.040s	1.221ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.498m	1.298ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.040s	1.221ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.097m	7.862ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1036	1040	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.41	100.00	97.91	100.00	100.00	99.72	99.70	98.52

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 22.sram_ctrl_bijection.69040962561642642989960850065296020306401376847206149047187403551666232328136
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 41.sram_ctrl_stress_all_with_rand_reset.43503525211666574261247708499426627936627851491204602228692192937400356571675
    Line 290, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1089417473 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1089417473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 42.sram_ctrl_stress_all.27083517284374633698466982133398352964766326038801134094848850752151275438536
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:4f6e3215-6279-4bdd-ab0e-bd7d7d736459
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 49.sram_ctrl_executable.62605985754026611730306560801075727420254414428945673121516486530142014453738
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 32483121460 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x2eece996
  UVM_INFO @ 32483121460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e3ca274e77`