SRAM_CTRL/MAIN Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.346m	456.812us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	84.127us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	26.303us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.210s	700.704us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	20.531us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.190s	2.188ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	26.303us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	20.531us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.390m	20.633ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.920m	18.163ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	41.577m	42.061ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.041m	14.000ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	49.158m	661.531ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	44.684m	59.501ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.111m	234.533ms	50	50	100.00
V2	executable	sram_ctrl_executable	32.996m	31.681ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.463m	1.413ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.867m	90.313ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.564m	6.952ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.906m	803.900us	50	50	100.00
V2	regwen	sram_ctrl_regwen	29.380m	46.218ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.520s	3.740ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.884h	947.792ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.740s	46.248us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.740s	136.135us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.740s	136.135us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	84.127us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	26.303us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	20.531us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	23.949us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	84.127us	5	5	100.00
		sram_ctrl_csr_rw	0.680s	26.303us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	20.531us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	23.949us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	54.330s	14.108ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.720s	847.290us	5	5	100.00
		sram_ctrl_tl_intg_err	2.470s	1.185ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.720s	847.290us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.470s	1.185ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	29.380m	46.218ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	26.303us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.996m	31.681ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.996m	31.681ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.996m	31.681ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.111m	234.533ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	54.330s	14.108ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.346m	456.812us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.346m	456.812us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.996m	31.681ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.720s	847.290us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.111m	234.533ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.720s	847.290us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.720s	847.290us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.346m	456.812us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.720s	847.290us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.211m	3.302ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1038	1040	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.12	99.81	97.23	100.00	100.00	98.61	99.70	98.52

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 0.sram_ctrl_stress_all.65862547018500296133543046350213720235774830036005693435435190482812717218427
      Line 285, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 58808740676 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xe36f079f
        UVM_INFO @ 58808740676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 27.sram_ctrl_stress_all.22641438738048219169313278014349626594548779699267194446166755367542013457232
      Line 299, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 94825591214 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xc2e256bc
        UVM_INFO @ 94825591214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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