SRAM_CTRL/MAIN Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.917m	5.644ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	60.698us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	12.980us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.870s	163.616us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.810s	24.269us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.730s	364.640us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	12.980us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	24.269us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.118m	187.797ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.789m	4.931ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	26.396m	27.214ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.741m	13.173ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	46.681m	175.881ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	27.949m	17.577ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.991m	220.942ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.575m	18.401ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.316m	13.610ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.340m	54.429ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.692m	779.864us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.745m	812.936us	50	50	100.00
V2	regwen	sram_ctrl_regwen	34.582m	261.789ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.930s	6.727ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.294h	776.145ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.690s	15.400us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.570s	671.683us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.570s	671.683us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	60.698us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	12.980us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	24.269us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.780s	107.600us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	60.698us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	12.980us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	24.269us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.780s	107.600us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	59.950s	78.141ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.400s	950.589us	5	5	100.00
		sram_ctrl_tl_intg_err	2.710s	652.636us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.400s	950.589us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.710s	652.636us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	34.582m	261.789ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	12.980us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.575m	18.401ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.575m	18.401ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.575m	18.401ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.991m	220.942ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	59.950s	78.141ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.917m	5.644ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.917m	5.644ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.575m	18.401ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.400s	950.589us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.991m	220.942ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.400s	950.589us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.400s	950.589us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.917m	5.644ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.400s	950.589us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.583m	8.326ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.81	97.15	100.00	100.00	98.61	99.70	98.52

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_bijection has 1 failures.

    • 8.sram_ctrl_bijection.111787751170050427385576191804219034129564725557002450723344105657737347490001
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 11.sram_ctrl_stress_all.27588710075593368621772525585347088000236510407235989389109232861050145622145
      Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 37115634267 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xe8139d7c
        UVM_INFO @ 37115634267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_regwen has 1 failures.

    • 16.sram_ctrl_regwen.24739975087301177331414009108375281689763050720063150590657830909937850121124
      Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_regwen/latest/run.log

        UVM_FATAL @ 30964005530 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xcc690b08
        UVM_INFO @ 30964005530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_executable has 1 failures.

    • 17.sram_ctrl_executable.23443400144738416695141229322514868701064125621754721183884851505762486196800
      Line 318, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/17.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 221524441427 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x34e3eba
        UVM_INFO @ 221524441427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.sram_ctrl_stress_all_with_rand_reset.110350073570438756860886276545541301465475487231353911616835053315539357968946
      Line 301, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2323133979 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2323133979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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