SRAM_CTRL/MAIN Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.743m 836.302us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.780s 36.835us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.760s 15.167us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.320s 336.621us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.750s 18.703us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.640s 2.543ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.760s 15.167us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 18.703us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 5.650m 42.186ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.846m 33.580ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 34.094m 191.874ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.179m 18.919ms 50 50 100.00
V2 bijection sram_ctrl_bijection 44.782m 460.230ms 47 50 94.00
V2 access_during_key_req sram_ctrl_access_during_key_req 27.134m 14.568ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.339m 338.251ms 50 50 100.00
V2 executable sram_ctrl_executable 29.873m 57.561ms 47 50 94.00
V2 partial_access sram_ctrl_partial_access 2.797m 4.712ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.790m 99.548ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.794m 12.683ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.666m 3.257ms 50 50 100.00
V2 regwen sram_ctrl_regwen 28.733m 29.037ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 5.100s 6.743ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.431h 472.423ms 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.720s 75.125us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.970s 687.200us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.970s 687.200us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.780s 36.835us 5 5 100.00
sram_ctrl_csr_rw 0.760s 15.167us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 18.703us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.910s 102.011us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.780s 36.835us 5 5 100.00
sram_ctrl_csr_rw 0.760s 15.167us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 18.703us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.910s 102.011us 20 20 100.00
V2 TOTAL 731 740 98.78
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.013m 54.279ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.540s 296.808us 5 5 100.00
sram_ctrl_tl_intg_err 2.720s 393.744us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.540s 296.808us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.720s 393.744us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 28.733m 29.037ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.760s 15.167us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 29.873m 57.561ms 47 50 94.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 29.873m 57.561ms 47 50 94.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 29.873m 57.561ms 47 50 94.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.339m 338.251ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.013m 54.279ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.743m 836.302us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.743m 836.302us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 29.873m 57.561ms 47 50 94.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.540s 296.808us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.339m 338.251ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.540s 296.808us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.540s 296.808us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.743m 836.302us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.540s 296.808us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 4.921m 12.289ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1030 1040 99.04

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.11 99.81 97.15 100.00 100.00 98.61 99.70 98.52

Failure Buckets

Past Results