SRAM_CTRL/MAIN Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.154m	3.094ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	27.238us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	51.243us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.450s	1.900ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.790s	128.916us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.940s	1.405ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	51.243us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	128.916us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.506m	103.230ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.638m	62.254ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	30.111m	26.850ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.711m	6.966ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	52.199m	782.939ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	34.550m	19.834ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.796m	182.302ms	50	50	100.00
V2	executable	sram_ctrl_executable	31.276m	110.545ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.630m	2.007ms	50	50	100.00
		sram_ctrl_partial_access_b2b	12.081m	132.102ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.322m	807.470us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.863m	821.979us	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.433m	2.819ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.900s	5.604ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.634h	1.325s	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.740s	23.292us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.940s	177.398us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.940s	177.398us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	27.238us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	51.243us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	128.916us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	31.174us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	27.238us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	51.243us	20	20	100.00
		sram_ctrl_csr_aliasing	0.790s	128.916us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	31.174us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	59.660s	28.320ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.730s	939.206us	5	5	100.00
		sram_ctrl_tl_intg_err	2.540s	277.674us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.730s	939.206us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.540s	277.674us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.433m	2.819ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	51.243us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	31.276m	110.545ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	31.276m	110.545ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	31.276m	110.545ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.796m	182.302ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	59.660s	28.320ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.154m	3.094ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.154m	3.094ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	31.276m	110.545ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.730s	939.206us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.796m	182.302ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.730s	939.206us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.730s	939.206us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.154m	3.094ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.730s	939.206us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.982m	8.585ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			1032	1040	99.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.81	97.15	100.00	100.00	98.61	99.70	98.52

Failure Buckets

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 3 failures:

Test sram_ctrl_stress_all has 3 failures.

18.sram_ctrl_stress_all.26289226861180214367236701574449182038852622762882329907245055398532907510631
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 1656312342 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 1656312342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.sram_ctrl_stress_all.106547043889638670903911265272931373020215392392840707603726244437918745105774
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 1999904452 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 1999904452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 14.sram_ctrl_stress_all_with_rand_reset.36328510914883640694390274712099498515723599790062468080156143202896806705558
    Line 351, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2405819801 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2405819801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.sram_ctrl_stress_all_with_rand_reset.71773806402582339873560037744066412871472284530334606507579501236426974636943
    Line 305, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3735905598 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3735905598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.sram_ctrl_stress_all_with_rand_reset.61573340896207919489681589975857157467498291175152347002205880764029558250289
    Line 297, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 19081774212 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x3d061606
  UVM_INFO @ 19081774212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 26.sram_ctrl_multiple_keys.52087492319503485429960274648126761670058195503041788450227201020616498781905
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 20973364877 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x82dad9ac
  UVM_INFO @ 20973364877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 37.sram_ctrl_bijection.16145219283126099454403073883486077273865457992056723989889704315788480137264
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/37.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```