SRAM_CTRL/MAIN Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: 1fbe1ece8d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.012m	3.432ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	54.270us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	27.906us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.850s	84.310us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	31.569us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.050s	374.199us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	27.906us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	31.569us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.345m	98.443ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.538m	25.257ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	36.366m	78.256ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.623m	6.797ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	44.963m	632.380ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	27.354m	67.934ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.456m	226.322ms	50	50	100.00
V2	executable	sram_ctrl_executable	40.740m	46.684ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.530m	5.273ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.100m	27.041ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.637m	771.624us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.194m	1.588ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.483m	27.430ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.500s	4.208ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.779h	323.398ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.690s	35.578us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.470s	563.162us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.470s	563.162us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	54.270us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	27.906us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	31.569us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	21.303us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	54.270us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	27.906us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	31.569us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	21.303us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	56.900s	29.291ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.320s	1.056ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.600s	615.145us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.320s	1.056ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.600s	615.145us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.483m	27.430ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	27.906us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	40.740m	46.684ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	40.740m	46.684ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	40.740m	46.684ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.456m	226.322ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	56.900s	29.291ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.012m	3.432ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.012m	3.432ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	40.740m	46.684ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.320s	1.056ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.456m	226.322ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.320s	1.056ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.320s	1.056ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.012m	3.432ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.320s	1.056ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.994m	4.609ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1039	1040	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.81	97.15	100.00	100.00	98.61	99.70	98.52

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
  • Test sram_ctrl_executable has 1 failures.

    • 33.sram_ctrl_executable.85735325281927195985276061695753223973578197688820086958006306170609350592857
      Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 23177595740 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xb711fd1f
        UVM_INFO @ 23177595740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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