SRAM_CTRL/MAIN Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.582m 2.549ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.710s 28.656us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 20.159us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.360s 161.962us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.830s 306.580us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.690s 7.048ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 20.159us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 306.580us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 5.306m 158.798ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.674m 57.039ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 23.416m 30.018ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 8.139m 14.198ms 50 50 100.00
V2 bijection sram_ctrl_bijection 43.838m 318.247ms 48 50 96.00
V2 access_during_key_req sram_ctrl_access_during_key_req 29.490m 20.155ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.724m 48.101ms 50 50 100.00
V2 executable sram_ctrl_executable 27.066m 27.114ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 1.492m 1.358ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.590m 101.370ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.647m 2.385ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 1.890m 3.106ms 50 50 100.00
V2 regwen sram_ctrl_regwen 25.869m 46.937ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 5.220s 6.670ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.551h 364.565ms 49 50 98.00
V2 alert_test sram_ctrl_alert_test 0.690s 43.755us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.650s 152.938us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.650s 152.938us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.710s 28.656us 5 5 100.00
sram_ctrl_csr_rw 0.730s 20.159us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 306.580us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.780s 199.429us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.710s 28.656us 5 5 100.00
sram_ctrl_csr_rw 0.730s 20.159us 20 20 100.00
sram_ctrl_csr_aliasing 0.830s 306.580us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.780s 199.429us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.024m 140.638ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.230s 1.097ms 5 5 100.00
sram_ctrl_tl_intg_err 2.660s 301.536us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.230s 1.097ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.660s 301.536us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 25.869m 46.937ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 20.159us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 27.066m 27.114ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 27.066m 27.114ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 27.066m 27.114ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.724m 48.101ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.024m 140.638ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.582m 2.549ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.582m 2.549ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 27.066m 27.114ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.230s 1.097ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.724m 48.101ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.230s 1.097ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.230s 1.097ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.582m 2.549ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.230s 1.097ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 3.247m 2.601ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1037 1040 99.71

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.11 99.81 97.15 100.00 100.00 98.61 99.70 98.52

Failure Buckets

Past Results