SRAM_CTRL/MAIN Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.209m	473.611us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.750s	24.849us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.760s	14.148us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.350s	663.962us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	39.021us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.810s	1.457ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.760s	14.148us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	39.021us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.599m	105.827ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.673m	20.391ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	28.347m	46.831ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.103m	106.053ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	47.824m	331.068ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	26.075m	72.851ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.827m	16.023ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.877m	79.975ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.766m	2.908ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.838m	42.861ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.738m	2.640ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.684m	3.265ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.561m	75.017ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.230s	5.614ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.163h	226.230ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.710s	43.385us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.530s	746.697us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.530s	746.697us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.750s	24.849us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	14.148us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	39.021us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	21.055us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.750s	24.849us	5	5	100.00
		sram_ctrl_csr_rw	0.760s	14.148us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	39.021us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	21.055us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.173m	140.815ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.300s	675.269us	5	5	100.00
		sram_ctrl_tl_intg_err	2.430s	762.755us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.300s	675.269us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.430s	762.755us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.561m	75.017ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.760s	14.148us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.877m	79.975ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.877m	79.975ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.877m	79.975ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.827m	16.023ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.173m	140.815ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.209m	473.611us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.209m	473.611us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.877m	79.975ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.300s	675.269us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.827m	16.023ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.300s	675.269us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.300s	675.269us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.209m	473.611us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.300s	675.269us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.056m	10.830ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1036	1040	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.11	99.81	97.15	100.00	100.00	98.61	99.70	98.52

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test sram_ctrl_bijection has 2 failures.

    • 12.sram_ctrl_bijection.99539998122129798754385151850981387359711144437503973349804069670198665192170
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 31.sram_ctrl_bijection.58202945341118563399464628354368035310981294725827381429635015187924646643508
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/31.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 5.sram_ctrl_multiple_keys.83148652196044062029218208284318754457836314588204733037733047302492692567665
      Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 15520931792 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x228eab98
        UVM_INFO @ 15520931792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 20.sram_ctrl_stress_all.108698972781666115480690667172589579526248087915650613034476712606438833334648
      Line 295, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 296960487167 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xa16563a3
        UVM_INFO @ 296960487167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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