SRAM_CTRL/MAIN Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.441m	5.010ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	24.696us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	32.179us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.530s	649.128us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	60.565us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.280s	367.715us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	32.179us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	60.565us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.574m	42.135ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.843m	31.073ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	30.904m	138.236ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.092m	23.087ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	49.094m	788.327ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	37.804m	96.213ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.930m	193.976ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.760m	213.186ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.512m	1.631ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.425m	99.863ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.779m	6.926ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.789m	5.561ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	24.221m	15.382ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.610s	4.195ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.157h	306.962ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.730s	14.352us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.280s	119.597us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.280s	119.597us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	24.696us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	32.179us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	60.565us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	156.691us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	24.696us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	32.179us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	60.565us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.850s	156.691us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.120m	44.013ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.490s	971.930us	5	5	100.00
		sram_ctrl_tl_intg_err	3.600s	4.286ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.490s	971.930us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.600s	4.286ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.221m	15.382ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	32.179us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.760m	213.186ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.760m	213.186ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.760m	213.186ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.930m	193.976ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.120m	44.013ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.441m	5.010ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.441m	5.010ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.760m	213.186ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.490s	971.930us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.930m	193.976ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.490s	971.930us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.490s	971.930us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.441m	5.010ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.490s	971.930us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.277m	3.873ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1039	1040	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	97.02	100.00	100.00	98.61	99.70	98.52

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test sram_ctrl_bijection has 1 failures.

    • 8.sram_ctrl_bijection.18694791347653246722641036938692262002502142484922394960810095946869950712315
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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