SRAM_CTRL/MAIN Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.924m	1.856ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	15.225us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	14.380us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.440s	508.053us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.810s	20.488us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.610s	6.787ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	14.380us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	20.488us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.338m	18.661ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.717m	32.224ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	29.288m	8.554ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.307m	26.410ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	47.626m	689.571ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	29.892m	81.773ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.914m	128.198ms	50	50	100.00
V2	executable	sram_ctrl_executable	34.738m	114.820ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	2.914m	5.638ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.869m	117.788ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.667m	1.502ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.467m	1.635ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	27.448m	21.416ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.940s	2.816ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.532h	94.128ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.690s	24.346us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.190s	567.103us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.190s	567.103us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	15.225us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	14.380us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	20.488us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	29.711us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	15.225us	5	5	100.00
		sram_ctrl_csr_rw	0.750s	14.380us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	20.488us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	29.711us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	57.400s	88.064ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.680s	477.625us	5	5	100.00
		sram_ctrl_tl_intg_err	2.660s	325.741us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.680s	477.625us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.660s	325.741us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	27.448m	21.416ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	14.380us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.738m	114.820ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.738m	114.820ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.738m	114.820ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.914m	128.198ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	57.400s	88.064ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.924m	1.856ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.924m	1.856ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.738m	114.820ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.680s	477.625us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.914m	128.198ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.680s	477.625us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.680s	477.625us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.924m	1.856ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.680s	477.625us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.956m	2.355ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1032	1040	99.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.07	99.81	97.02	100.00	100.00	98.61	99.70	98.33

Failure Buckets

UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_executable has 2 failures.
  - 1.sram_ctrl_executable.29781171633033937256458500565085514280758365173956076668304752318878787165000
    Line 302, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 222479150135 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x9eaa4c6d
  UVM_INFO @ 222479150135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.sram_ctrl_executable.52028596113713087697022639079973534936228735543348630827190006159431273920300
    Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 98642853988 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x135b9c8a
  UVM_INFO @ 98642853988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_regwen has 2 failures.
  - 13.sram_ctrl_regwen.48898421238437071421443631161736482691389253637819867233924085426957554669594
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 23398657871 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x711a2c94
  UVM_INFO @ 23398657871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.sram_ctrl_regwen.109244813671191838873019210841582047667089176460216894997310295998090706015516
    Line 322, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/33.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 219224363164 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x480840b7
  UVM_INFO @ 219224363164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test sram_ctrl_bijection has 2 failures.
  - 15.sram_ctrl_bijection.81876275606468935320079343428267898207269720767082400971965521431575462956566
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.sram_ctrl_bijection.90223847049470922512175281702251705364324534763468916312486390512634695683485
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 41.sram_ctrl_stress_all_with_rand_reset.14695975279325671565161508971211591487066788162036764483735870617769214340136
    Line 299, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2084373478 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2084373478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 49.sram_ctrl_stress_all.46973346638629137177638883850700270457370143180081074381276906748049224541285
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:3f09e662-3a63-4fb3-8a6c-3419e849ef74
```

SRAM_CTRL/MAIN Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d3942ca074`