SRAM_CTRL/MAIN Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.432m	4.307ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	39.719us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	45.990us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.000s	455.495us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	60.310us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.030s	3.882ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	45.990us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	60.310us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.256m	43.024ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.675m	20.738ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	41.377m	104.168ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.391m	5.370ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	53.660m	218.222ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	38.554m	18.972ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.873m	86.511ms	50	50	100.00
V2	executable	sram_ctrl_executable	50.521m	91.564ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.952m	5.515ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.781m	125.229ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.427m	1.148ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.355m	1.636ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	41.116m	69.702ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.620s	4.179ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.588h	109.777ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.690s	44.095us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.450s	127.426us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.450s	127.426us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	39.719us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	45.990us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	60.310us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	45.221us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	39.719us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	45.990us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	60.310us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	45.221us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	59.570s	29.403ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.520s	1.346ms	5	5	100.00
		sram_ctrl_tl_intg_err	2.440s	341.232us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.520s	1.346ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.440s	341.232us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	41.116m	69.702ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	45.990us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	50.521m	91.564ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	50.521m	91.564ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	50.521m	91.564ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.873m	86.511ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	59.570s	29.403ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.432m	4.307ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.432m	4.307ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	50.521m	91.564ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.520s	1.346ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.873m	86.511ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.520s	1.346ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.520s	1.346ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.432m	4.307ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.520s	1.346ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.948m	5.147ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	96.99	100.00	100.00	98.60	99.70	98.52

Failure Buckets

Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test sram_ctrl_stress_all has 2 failures.
  - 9.sram_ctrl_stress_all.14786787119640308047532368287134512155120205791137909419154503266887278364800
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:f97b7b18-d001-46d5-a196-01f0a92757b0
```
  - 36.sram_ctrl_stress_all.113564744905355535197688225660781781521750884680217001163068712677117763161717
    Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all/latest/run.log
```
  Job ID: smart:47c0315b-6c26-4266-ab0b-8753bf8e593d
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 18.sram_ctrl_regwen.13202622223126648425956813745708604026929945261761724370258626312946936748400
    Line 285, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/18.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 57643943044 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xaa47017d
  UVM_INFO @ 57643943044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 38.sram_ctrl_stress_all_with_rand_reset.47941075216855286118059928530243147132023897802585831794809433558421402686848
    Line 330, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1575398643 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1575398643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 38.sram_ctrl_stress_all.47446827780527628610031963196792274564647584775231527285113338215682920414243
    Line 313, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 1394717848767 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xd1ced003
  UVM_INFO @ 1394717848767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/MAIN Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4fd94db59a`