SRAM_CTRL/MAIN Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.792m	6.145ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	26.489us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	24.991us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.220s	169.792us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	76.558us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.350s	1.440ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	24.991us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	76.558us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.824m	43.083ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.863m	8.905ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	35.506m	31.032ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.146m	12.613ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	50.606m	830.084ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	32.120m	87.082ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.054m	290.049ms	50	50	100.00
V2	executable	sram_ctrl_executable	30.874m	20.466ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.880m	546.800us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.900m	92.617ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.724m	767.840us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.733m	3.540ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	42.737m	45.973ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.240s	5.596ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.550h	115.387ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	0.710s	29.242us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.480s	1.531ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.480s	1.531ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	26.489us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	24.991us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	76.558us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	50.802us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	26.489us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	24.991us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	76.558us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	50.802us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.180m	58.794ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.810s	422.968us	5	5	100.00
		sram_ctrl_tl_intg_err	2.680s	397.059us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.810s	422.968us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.680s	397.059us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	42.737m	45.973ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	24.991us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.874m	20.466ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.874m	20.466ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.874m	20.466ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.054m	290.049ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.180m	58.794ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.792m	6.145ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.792m	6.145ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.874m	20.466ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.810s	422.968us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.054m	290.049ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.810s	422.968us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.810s	422.968us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.792m	6.145ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.810s	422.968us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.403m	4.962ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1037	1040	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	96.99	100.00	100.00	98.60	99.70	98.52

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test sram_ctrl_bijection has 2 failures.

    • 15.sram_ctrl_bijection.105025213638691951571307828399824145631799013778003966846521551224950356999646
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/15.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.sram_ctrl_bijection.87109260967036333624630580002032682272177778115208150728227947419628788464354
      Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job sram_ctrl_main-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 26.sram_ctrl_stress_all.110248994709738426384453170766593320798474330655582840107104799412693194711803
      Log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest/run.log

        Job ID: smart:ac1dc472-a0d5-47a8-aa05-2a2a50a9e4b1
      

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