SRAM_CTRL/MAIN Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.844m 2.142ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.760s 29.122us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.710s 14.549us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.190s 276.189us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.730s 32.281us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.440s 1.390ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.710s 14.549us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 32.281us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 5.849m 147.526ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 2.558m 9.486ms 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 32.632m 27.998ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.814m 6.132ms 50 50 100.00
V2 bijection sram_ctrl_bijection 46.638m 181.469ms 48 50 96.00
V2 access_during_key_req sram_ctrl_access_during_key_req 36.480m 104.243ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 2.995m 275.370ms 50 50 100.00
V2 executable sram_ctrl_executable 29.925m 69.539ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.578m 2.670ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.602m 448.033ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.712m 3.060ms 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.787m 803.950us 50 50 100.00
V2 regwen sram_ctrl_regwen 22.537m 89.527ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 3.770s 3.369ms 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.244h 588.949ms 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.730s 45.567us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.270s 636.252us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.270s 636.252us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.760s 29.122us 5 5 100.00
sram_ctrl_csr_rw 0.710s 14.549us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 32.281us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 17.216us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.760s 29.122us 5 5 100.00
sram_ctrl_csr_rw 0.710s 14.549us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 32.281us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.820s 17.216us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 1.022m 29.432ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.320s 1.661ms 5 5 100.00
sram_ctrl_tl_intg_err 2.460s 381.102us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.320s 1.661ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.460s 381.102us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 22.537m 89.527ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.710s 14.549us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 29.925m 69.539ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 29.925m 69.539ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 29.925m 69.539ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 2.995m 275.370ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 1.022m 29.432ms 20 20 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.844m 2.142ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.844m 2.142ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 29.925m 69.539ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.320s 1.661ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 2.995m 275.370ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.320s 1.661ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.320s 1.661ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.844m 2.142ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.320s 1.661ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 4.310m 2.252ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1035 1040 99.52

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.09 99.81 96.99 100.00 100.00 98.60 99.70 98.52

Failure Buckets

Past Results